commit 498231bc601013da055fb8786d091b743c20006a
author Brian Gaeke <gaeke@uiuc.edu> Thu Jun 03 02:45:09 2004 +0000
committer Brian Gaeke <gaeke@uiuc.edu> Thu Jun 03 02:45:09 2004 +0000
tree 692dde500b4fcafc20bcff73fdca856e3d73fd39
parent 44afcb7dcf3036bec35f4c4e2f85141bc966c418

Collapse together the abstract superclass TargetRegInfo and SparcV9RegInfo, its
only concrete implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13977 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SparcV9/SparcV9CodeEmitter.cpp

diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index a11594e..631db7c 100644
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -474,7 +474,7 @@
 unsigned 
 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
                                   MachineInstr &MI) {
-  const TargetRegInfo &RI = *TM.getRegInfo();
+  const SparcV9RegInfo &RI = *TM.getRegInfo();
   unsigned regClass, regType = RI.getRegType(fakeReg);
   // At least map fakeReg into its class
   fakeReg = RI.getClassRegNum(fakeReg, regClass);