| commit | 78a4f23a8e2c14d708899d1bd2011b64584fafa7 | [log] [tgz] |
|---|---|---|
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | Tue May 27 00:02:22 2003 +0000 |
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | Tue May 27 00:02:22 2003 +0000 |
| tree | 4ae33406a650cb1e4ca23480f3e805f296d5f463 | |
| parent | bd4ecf769def9fff84ab27e6467e5510105caf99 [diff] |
Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6339 91177308-0d34-0410-b5e6-96231b3b80d8