Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 8ef541f..a773916 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1284,7 +1284,7 @@
MVT HalfVT;
unsigned Opc = 0;
switch (VT.getVectorElementType().getSimpleVT()) {
- default: assert(false && "unhandled VDUP splat type");
+ default: llvm_unreachable("unhandled VDUP splat type");
case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
@@ -1304,6 +1304,62 @@
break;
}
+
+ case ARMISD::VLD2D: {
+ MVT VT = Op.getValueType();
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ unsigned Opc;
+ switch (VT.getSimpleVT()) {
+ default: llvm_unreachable("unhandled VLD2D type");
+ case MVT::v8i8: Opc = ARM::VLD2d8; break;
+ case MVT::v4i16: Opc = ARM::VLD2d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD2d32; break;
+ case MVT::v1i64: Opc = ARM::VLD2d64; break;
+ }
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
+ }
+
+ case ARMISD::VLD3D: {
+ MVT VT = Op.getValueType();
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ unsigned Opc;
+ switch (VT.getSimpleVT()) {
+ default: llvm_unreachable("unhandled VLD3D type");
+ case MVT::v8i8: Opc = ARM::VLD3d8; break;
+ case MVT::v4i16: Opc = ARM::VLD3d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD3d32; break;
+ case MVT::v1i64: Opc = ARM::VLD3d64; break;
+ }
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
+ }
+
+ case ARMISD::VLD4D: {
+ MVT VT = Op.getValueType();
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ unsigned Opc;
+ switch (VT.getSimpleVT()) {
+ default: llvm_unreachable("unhandled VLD4D type");
+ case MVT::v8i8: Opc = ARM::VLD4d8; break;
+ case MVT::v4i16: Opc = ARM::VLD4d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD4d32; break;
+ case MVT::v1i64: Opc = ARM::VLD4d64; break;
+ }
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
+ std::vector<MVT> ResTys(4, VT);
+ ResTys.push_back(MVT::Other);
+ return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
+ }
}
return SelectCode(Op);