Use TRI::printReg instead of AbstractRegisterDescription when printing
LiveIntervalUnions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index eb1b907..a5e5f1f 100644
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -60,14 +60,6 @@
const char *RegAllocBase::TimerGroupName = "Register Allocation";
namespace {
-
-class PhysicalRegisterDescription : public AbstractRegisterDescription {
- const TargetRegisterInfo *TRI;
-public:
- PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
- virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
-};
-
/// RABasic provides a minimal implementation of the basic register allocation
/// algorithm. It prioritizes live virtual registers by spill weight and spills
/// whenever a register is unavailable. This is not practical in production but
@@ -165,8 +157,7 @@
// Verify disjoint unions.
for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
- DEBUG(PhysicalRegisterDescription PRD(TRI);
- PhysReg2LiveUnion[PhysReg].dump(&PRD));
+ DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
PhysReg2LiveUnion[PhysReg].verify(VRegs);
// Union + intersection test could be done efficiently in one pass, but