Update the names of the exception handling sjlj instrinsics to
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index f5b33b0..d3cf667 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1045,8 +1045,8 @@
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer:
return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
- case Intrinsic::builtinsetjmp:
- SDValue Res = DAG.getNode(ARMISD::BUILTIN_SETJMP, dl, MVT::i32,
+ case Intrinsic::eh_sjlj_setjmp:
+ SDValue Res = DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32,
Op.getOperand(1));
return Res;
}
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 3243412..0bd492f 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -64,8 +64,8 @@
FMRRD, // double to two gprs.
FMDRR, // Two gprs to double.
- BUILTIN_SETJMP, // exception handling setjmp
- BUILTIN_LONGJMP, // exception handling longjmp
+ EH_SJLJ_SETJMP, // SjLj exception handling setjmp
+ EH_SJLJ_LONGJMP, // SjLj exception handling longjmp
THREAD_POINTER
};
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 8e678a8..4b0dbb5 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -991,7 +991,7 @@
// If this machine instr is a constant pool entry, its size is recorded as
// operand #2.
return MI->getOperand(2).getImm();
- case ARM::Int_builtin_setjmp: return 12;
+ case ARM::Int_eh_sjlj_setjmp: return 12;
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd:
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index cdc0ee5..d2e4c34 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -40,7 +40,7 @@
SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
-def SDT_ARMBuiltinSetjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
+def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
// Node definitions.
def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
@@ -85,7 +85,7 @@
def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
-def ARMbuiltin_setjmp: SDNode<"ARMISD::BUILTIN_SETJMP", SDT_ARMBuiltinSetjmp>;
+def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
//===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions.
@@ -1269,23 +1269,25 @@
//===----------------------------------------------------------------------===//
// SJLJ Exception handling intrinsics
-// setjmp() is a three instruction sequence to store the return address
-// and save #0 in R0 for the non-longjmp case.
+// eh_sjlj_setjmp() is a three instruction sequence to store the return
+// address and save #0 in R0 for the non-longjmp case.
// Since by its nature we may be coming from some other function to get
// here, and we're using the stack frame for the containing function to
// save/restore registers, we can't keep anything live in regs across
-// the setjmp(), else it will almost certainly have been tromped upon
+// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
// when we get here from a longjmp(). We force everthing out of registers
-// except for our own input by listing the relevant registers in Defs.
+// except for our own input by listing the relevant registers in Defs. By
+// doing so, we also cause the prologue/epilogue code to actively preserve
+// all of the callee-saved resgisters, which is exactly what we want.
let Defs =
[ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
- def Int_builtin_setjmp : XI<(outs), (ins GPR:$src),
+ def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
"add r0, pc, #4\n\t"
"str r0, [$src, #+4]\n\t"
- "mov r0, #0 @ setjmp", "",
- [(set R0, (ARMbuiltin_setjmp GPR:$src))]>;
+ "mov r0, #0 @ eh_setjmp", "",
+ [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
}
//===----------------------------------------------------------------------===//