commit 4a95c199779037d1dc60db8f7b883e28c794b001
author Devang Patel <dpatel@apple.com> Wed Jan 26 21:41:22 2011 +0000
committer Devang Patel <dpatel@apple.com> Wed Jan 26 21:41:22 2011 +0000
tree ce92a977d49f805ee66048090881bb3842861352
parent 1f64ac403549413b7d5c735d8530257f8661943b

Revert 124301.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124327 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 2d7178b..4c9158a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -539,12 +539,8 @@
                     SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
                            SmallSet<unsigned, 8> &Seen) {
   unsigned Order = DAG->GetOrdering(N);
-  if (!Order || !Seen.insert(Order)) {
-    // Process any valid SDDbgValues even if node does not have any order
-    // assigned.
-    ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
+  if (!Order || !Seen.insert(Order))
     return;
-  }
 
   MachineBasicBlock *BB = Emitter.getBlock();
   if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {