Add support for the 'l' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 854cfab..ca0472b 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -3001,6 +3001,7 @@
// backwards compatibility.
// 'c' : A register suitable for use in an indirect
// jump. This will always be $25 for -mabicalls.
+ // 'l' : The lo register.
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;
@@ -3008,6 +3009,7 @@
case 'y':
case 'f':
case 'c':
+ case 'l':
return C_RegisterClass;
}
}
@@ -3042,6 +3044,7 @@
weight = CW_Register;
break;
case 'c': // $25 for indirect jumps
+ case 'l': // lo register
if (type->isIntegerTy())
weight = CW_SpecificReg;
break;
@@ -3090,6 +3093,10 @@
return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
assert(VT == MVT::i64 && "Unexpected type.");
return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
+ case 'l': // register suitable for indirect jump
+ if (VT == MVT::i32)
+ return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
+ return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
}
}
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);