Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 4da5496..8fdbe9b 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -128,6 +128,9 @@
/// AA - AliasAnalysis for making memory reference queries.
AliasAnalysis *AA;
+ /// AntiDepMode - Anti-dependence breaking mode
+ TargetSubtarget::AntiDepBreakMode AntiDepMode;
+
/// Classes - For live regs that are only used in one register class in a
/// live range, the register class. If the register is not live, the
/// corresponding value is null. If the register is live but used in
@@ -156,10 +159,11 @@
const MachineLoopInfo &MLI,
const MachineDominatorTree &MDT,
ScheduleHazardRecognizer *HR,
- AliasAnalysis *aa)
+ AliasAnalysis *aa,
+ TargetSubtarget::AntiDepBreakMode adm)
: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
AllocatableSet(TRI->getAllocatableSet(MF)),
- HazardRec(HR), AA(aa) {}
+ HazardRec(HR), AA(aa), AntiDepMode(adm) {}
~SchedulePostRATDList() {
delete HazardRec;
@@ -234,16 +238,23 @@
AA = &getAnalysis<AliasAnalysis>();
// Check for explicit enable/disable of post-ra scheduling.
+ TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
if (EnablePostRAScheduler.getPosition() > 0) {
if (!EnablePostRAScheduler)
return false;
} else {
// Check that post-RA scheduling is enabled for this target.
const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
- if (!ST.enablePostRAScheduler(OptLevel))
+ if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode))
return false;
}
+ // Check for antidep breaking override...
+ if (EnableAntiDepBreaking.getPosition() > 0) {
+ AntiDepMode = (EnableAntiDepBreaking) ?
+ TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
+ }
+
DEBUG(errs() << "PostRAScheduler\n");
const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
@@ -253,7 +264,7 @@
(ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
- SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA);
+ SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA, AntiDepMode);
// Loop over all of the basic blocks
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
@@ -393,7 +404,7 @@
// Build the scheduling graph.
BuildSchedGraph(AA);
- if (EnableAntiDepBreaking) {
+ if (AntiDepMode != TargetSubtarget::ANTIDEP_NONE) {
if (BreakAntiDependencies()) {
// We made changes. Update the dependency graph.
// Theoretically we could update the graph in place:
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index bc5768e..7478159 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -128,7 +128,9 @@
/// enablePostRAScheduler - True at 'More' optimization except
/// for Thumb1.
- bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+ TargetSubtarget::AntiDepBreakMode& mode) const {
+ mode = TargetSubtarget::ANTIDEP_NONE;
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index 27e4333..0e4cfde 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -218,7 +218,9 @@
/// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
/// at 'More' optimization level.
- bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+ TargetSubtarget::AntiDepBreakMode& mode) const {
+ mode = TargetSubtarget::ANTIDEP_NONE;
return OptLevel >= CodeGenOpt::Default;
}
};