Update gcc 4.3 warnings fix patch with recent head changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47368 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 026666c..cd57d3a 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1996,11 +1996,12 @@
LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
- if (SUBC->getValue() == OpSizeInBits)
+ if (SUBC->getValue() == OpSizeInBits) {
if (HasROTL)
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+ }
}
}
@@ -2010,11 +2011,12 @@
RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
- if (SUBC->getValue() == OpSizeInBits)
+ if (SUBC->getValue() == OpSizeInBits) {
if (HasROTL)
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+ }
}
}
@@ -2230,7 +2232,7 @@
// the constant which would cause it to be modified for this
// operation.
if (N->getOpcode() == ISD::SRA) {
- uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
+ uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1);
if ((bool)BinOpRHSSign != HighBitSet)
return SDOperand();
}
@@ -2552,7 +2554,7 @@
return SDOperand(N, 0); // Don't revisit N.
// fold selects based on a setcc into other things, such as min/max/abs
- if (N0.getOpcode() == ISD::SETCC)
+ if (N0.getOpcode() == ISD::SETCC) {
// FIXME:
// Check against MVT::Other for SELECT_CC, which is a workaround for targets
// having to say they don't support SELECT_CC on every type the DAG knows
@@ -2562,6 +2564,7 @@
N1, N2, N0.getOperand(2));
else
return SimplifySelect(N0, N1, N2);
+ }
return SDOperand();
}
@@ -4013,8 +4016,8 @@
if (!((Use->getOpcode() == ISD::LOAD &&
cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
- (Use->getOpcode() == ISD::STORE) &&
- cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
+ (Use->getOpcode() == ISD::STORE &&
+ cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
RealUse = true;
}
if (!RealUse)
@@ -4131,8 +4134,8 @@
SDNode *UseUse = *III;
if (!((UseUse->getOpcode() == ISD::LOAD &&
cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
- (UseUse->getOpcode() == ISD::STORE) &&
- cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
+ (UseUse->getOpcode() == ISD::STORE &&
+ cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)))
RealUse = true;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 2cda597..17aaa75 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1269,15 +1269,18 @@
unsigned RScratch = calcMaxScratches(right);
if (LScratch > RScratch)
return true;
- else if (LScratch == RScratch)
+ else if (LScratch == RScratch) {
if (left->Height > right->Height)
return true;
- else if (left->Height == right->Height)
+ else if (left->Height == right->Height) {
if (left->Depth < right->Depth)
return true;
- else if (left->Depth == right->Depth)
+ else if (left->Depth == right->Depth) {
if (left->CycleBound > right->CycleBound)
return true;
+ }
+ }
+ }
}
}
return false;
@@ -1509,15 +1512,19 @@
if (LPriority+LBonus < RPriority+RBonus)
return true;
- else if (LPriority == RPriority)
+ else if (LPriority == RPriority) {
if (left->Depth < right->Depth)
return true;
- else if (left->Depth == right->Depth)
+ else if (left->Depth == right->Depth) {
if (left->NumSuccsLeft > right->NumSuccsLeft)
return true;
- else if (left->NumSuccsLeft == right->NumSuccsLeft)
+ else if (left->NumSuccsLeft == right->NumSuccsLeft) {
if (left->CycleBound > right->CycleBound)
return true;
+ }
+ }
+ }
+
return false;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index eb3729c..8a2962f 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1075,7 +1075,7 @@
}
}
}
- if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val))
+ if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
// No compile time operations on this type yet.
if (N1C->getValueType(0) == MVT::ppcf128)
@@ -1127,7 +1127,8 @@
// Ensure that the constant occurs on the RHS.
return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
}
-
+ }
+
// Could not fold it.
return SDOperand();
}
@@ -2334,20 +2335,22 @@
break;
}
case ISD::SELECT:
- if (N1C)
- if (N1C->getValue())
+ if (N1C) {
+ if (N1C->getValue())
return N2; // select true, X, Y -> X
else
return N3; // select false, X, Y -> Y
+ }
if (N2 == N3) return N2; // select C, X, X -> X
break;
case ISD::BRCOND:
- if (N2C)
+ if (N2C) {
if (N2C->getValue()) // Unconditional branch
return getNode(ISD::BR, MVT::Other, N1, N3);
else
return N1; // Never-taken branch
+ }
break;
case ISD::VECTOR_SHUFFLE:
assert(VT == N1.getValueType() && VT == N2.getValueType() &&
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 1ee93d7..001c9f6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2602,7 +2602,7 @@
static GlobalVariable *ExtractTypeInfo (Value *V) {
V = IntrinsicInst::StripPointerCasts(V);
GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
- assert (GV || isa<ConstantPointerNull>(V) &&
+ assert ((GV || isa<ConstantPointerNull>(V)) &&
"TypeInfo must be a global variable or NULL");
return GV;
}