Revert 56176. All those instruction formats are still needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 8302d77..7abb7d2 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -343,7 +343,8 @@
unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- if ((TID.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
+ unsigned Format = TID.TSFlags & ARMII::FormMask;
+ if (Format == ARMII::Pseudo)
abort(); // FIXME
// Encode S bit if MI modifies CPSR.
@@ -358,7 +359,14 @@
}
// Encode first non-shifter register operand if ther is one.
- if ((TID.TSFlags & ARMII::FormMask) != ARMII::UnaryFrm) {
+ bool isUnary = (Format == ARMII::DPRdMisc ||
+ Format == ARMII::DPRdIm ||
+ Format == ARMII::DPRdReg ||
+ Format == ARMII::DPRdSoReg ||
+ Format == ARMII::DPRnIm ||
+ Format == ARMII::DPRnReg ||
+ Format == ARMII::DPRnSoReg);
+ if (!isUnary) {
Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
++OpIdx;
}