commit 4cbe0662abb2cd6025eff51e19574a48f1a83b97
author Dan Gohman <gohman@apple.com> Wed Aug 20 18:10:48 2008 +0000
committer Dan Gohman <gohman@apple.com> Wed Aug 20 18:10:48 2008 +0000
tree bd1454aff181b6ac3996e932442f81f072ed53aa
parent 77ad79689d755c49146f534107421cb3d9703fed

Minor code reorganization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55071 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/FastISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 7cb888c..954de1d 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -146,8 +146,8 @@
 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
                                  const TargetRegisterClass* RC) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
   unsigned ResultReg = MRI.createVirtualRegister(RC);
+  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
 
   MachineInstr *MI = BuildMI(*MF, II, ResultReg);
 
@@ -159,8 +159,8 @@
                                   const TargetRegisterClass *RC,
                                   unsigned Op0) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
   unsigned ResultReg = MRI.createVirtualRegister(RC);
+  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
 
   MachineInstr *MI = BuildMI(*MF, II, ResultReg);
   MI->addOperand(MachineOperand::CreateReg(Op0, false));
@@ -173,8 +173,8 @@
                                    const TargetRegisterClass *RC,
                                    unsigned Op0, unsigned Op1) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
   unsigned ResultReg = MRI.createVirtualRegister(RC);
+  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
 
   MachineInstr *MI = BuildMI(*MF, II, ResultReg);
   MI->addOperand(MachineOperand::CreateReg(Op0, false));