Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
1 file changed