Don't reserve R2 on Darwin/PPC
Now that only the register-scavenger version of the CR spilling code remains,
we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in
any case where the System V ABI uses it (R0 is special architecturally, and so
is reserved under all common ABIs).
A few test cases needed to be updated to reflect the register-allocation changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
index 84aa40c..91253da 100644
--- a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
+++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
@@ -10,8 +10,8 @@
define void @foo(i32 %y) nounwind ssp {
entry:
; CHECK: foo
-; CHECK: add r3
-; CHECK: 0(r3)
+; CHECK: add r2
+; CHECK: 0(r2)
%y_addr = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %y, i32* %y_addr
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 974a99a..433fe5c 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -6,17 +6,17 @@
define void @foo() nounwind {
entry:
-;CHECK: mfcr r2
-;CHECK: lis r3, 1
-;CHECK: rlwinm r2, r2, 8, 0, 31
-;CHECK: ori r3, r3, 34524
-;CHECK: stwx r2, r1, r3
+;CHECK: mfcr r0
+;CHECK: lis r2, 1
+;CHECK: rlwinm r0, r0, 8, 0, 31
+;CHECK: ori r2, r2, 34524
+;CHECK: stwx r0, r1, r2
; Make sure that the register scavenger returns the same temporary register.
-;CHECK: mfcr r2
-;CHECK: lis r3, 1
-;CHECK: rlwinm r2, r2, 12, 0, 31
-;CHECK: ori r3, r3, 34520
-;CHECK: stwx r2, r1, r3
+;CHECK: lis r2, 1
+;CHECK: mfcr r0
+;CHECK: ori r2, r2, 34520
+;CHECK: rlwinm r0, r0, 12, 0, 31
+;CHECK: stwx r0, r1, r2
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
@@ -25,11 +25,11 @@
br label %return
return: ; preds = %entry
-;CHECK: lis r3, 1
-;CHECK: ori r3, r3, 34524
-;CHECK: lwzx r2, r1, r3
-;CHECK: rlwinm r2, r2, 24, 0, 31
-;CHECK: mtcrf 32, r2
+;CHECK: lis r2, 1
+;CHECK: ori r2, r2, 34524
+;CHECK: lwzx r0, r1, r2
+;CHECK: rlwinm r0, r0, 24, 0, 31
+;CHECK: mtcrf 32, r0
ret void
}
diff --git a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
index 72ae9d6..0dbc2d0 100644
--- a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
+++ b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
@@ -18,8 +18,8 @@
; CHECK: _g:
; CHECK: mflr r0
; CHECK: stw r0, 8(r1)
-; CHECK: lwz r3, 0(r1)
-; CHECK: lwz r3, 8(r3)
+; CHECK: lwz r2, 0(r1)
+; CHECK: lwz r3, 8(r2)
%0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1]
ret i8* %0
}
diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
index bf3d577..d1a3c9f 100644
--- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
+++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
@@ -7,7 +7,7 @@
entry:
; Make sure we're generating references using the red zone
; CHECK: main:
-; CHECK: stw r3, -12(r1)
+; CHECK: stw r2, -12(r1)
%retval = alloca i32
%0 = alloca i32
%"alloca point" = bitcast i32 0 to i32
diff --git a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
index 6f985c8..e8765de 100644
--- a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
+++ b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
@@ -1,9 +1,9 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
-; RUN: grep "stw r4, 32751"
+; RUN: grep "stw r3, 32751"
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
-; RUN: grep "stw r4, 32751"
+; RUN: grep "stw r3, 32751"
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
-; RUN: grep "std r4, 9024"
+; RUN: grep "std r3, 9024"
define void @test() nounwind {
store i32 0, i32* inttoptr (i64 48725999 to i32*)
diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll
index 1769be9..90f0480 100644
--- a/test/CodeGen/PowerPC/varargs.ll
+++ b/test/CodeGen/PowerPC/varargs.ll
@@ -8,15 +8,16 @@
}
; P32: test1:
-; P32: lwz r4, 0(r3)
-; P32: addi r5, r4, 4
-; P32: stw r5, 0(r3)
-; P32: lwz r3, 0(r4)
-; P32: blr
+; P32: lwz r2, 0(r3)
+; P32: addi r4, r2, 4
+; P32: stw r4, 0(r3)
+; P32: lwz r3, 0(r2)
+; P32: blr
; P64: test1:
-; P64: ld r4, 0(r3)
-; P64: addi r5, r4, 8
-; P64: std r5, 0(r3)
-; P64: ld r3, 0(r4)
-; P64: blr
+; P64: ld r2, 0(r3)
+; P64: addi r4, r2, 8
+; P64: std r4, 0(r3)
+; P64: ld r3, 0(r2)
+; P64: blr
+