diff --git a/lib/Analysis/LiveVar/BBLiveVar.cpp b/lib/Analysis/LiveVar/BBLiveVar.cpp
index 758f1b1..270fbbd 100644
--- a/lib/Analysis/LiveVar/BBLiveVar.cpp
+++ b/lib/Analysis/LiveVar/BBLiveVar.cpp
@@ -52,12 +52,12 @@
     // iterate over  MI operands to find defs
     for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end();
          OpI != OpE; ++OpI)
-      if (OpI.isDefOnly() || OpI.isDefAndUse()) // add to Defs if this operand is a def
+      if (OpI.isDef()) // add to Defs if this operand is a def
 	addDef(*OpI);
 
     // do for implicit operands as well
     for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i)
-      if (MI->getImplicitOp(i).opIsDefOnly() || MI->getImplicitOp(i).opIsDefAndUse())
+      if (MI->getImplicitOp(i).isDef())
 	addDef(MI->getImplicitRef(i));
     
     // iterate over MI operands to find uses
@@ -68,8 +68,7 @@
       if (isa<BasicBlock>(Op))
 	continue;             // don't process labels
 
-      if (OpI.isUseOnly() || OpI.isDefAndUse()) {
-                                // add to Uses only if this operand is a use
+      if (OpI.isUse()) { // add to Uses only if this operand is a use
         //
         // *** WARNING: The following code for handling dummy PHI machine
         //     instructions is untested.  The previous code was broken and I
@@ -104,7 +103,7 @@
       if (Op->getType() == Type::LabelTy)             // don't process labels
 	continue;
 
-      if (MI->getImplicitOp(i).opIsUse() || MI->getImplicitOp(i).opIsDefAndUse())
+      if (MI->getImplicitOp(i).isUse())
 	addUse(Op);
     }
   } // for all machine instructions
diff --git a/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp b/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
index 8f0e318..e342760 100644
--- a/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
+++ b/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
@@ -235,14 +235,13 @@
 static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
   for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
          OpE = MInst->end(); OpI != OpE; ++OpI) {
-    if (OpI.isDefOnly() || OpI.isDefAndUse()) // kill if this operand is a def
+    if (OpI.isDef())                          // kill if this operand is a def
       LVS.erase(*OpI);                        // this definition kills any uses
   }
 
   // do for implicit operands as well
   for (unsigned i=0; i < MInst->getNumImplicitRefs(); ++i) {
-    if (MInst->getImplicitOp(i).opIsDefOnly() ||
-        MInst->getImplicitOp(i).opIsDefAndUse())
+    if (MInst->getImplicitOp(i).isDef())
       LVS.erase(MInst->getImplicitRef(i));
   }
 
@@ -250,14 +249,13 @@
          OpE = MInst->end(); OpI != OpE; ++OpI) {
     if (!isa<BasicBlock>(*OpI))      // don't process labels
       // add only if this operand is a use
-      if (!OpI.isDefOnly() || OpI.isDefAndUse() )
+      if (OpI.isUse())
         LVS.insert(*OpI);            // An operand is a use - so add to use set
   }
 
   // do for implicit operands as well
   for (unsigned i = 0, e = MInst->getNumImplicitRefs(); i != e; ++i)
-    if (MInst->getImplicitOp(i).opIsUse() ||
-        MInst->getImplicitOp(i).opIsDefAndUse())
+    if (MInst->getImplicitOp(i).isUse())
       LVS.insert(MInst->getImplicitRef(i));
 }
 
diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 3a80880..2dafe62 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -342,8 +342,8 @@
       unsigned int opNum   = regRefVec[i].second;
       const MachineOperand& mop =
         node->getMachineInstr()->getExplOrImplOperand(opNum);
-      bool isDef = mop.opIsDefOnly();
-      bool isDefAndUse = mop.opIsDefAndUse();
+      bool isDef = mop.isDef() && !mop.isUse();
+      bool isDefAndUse = mop.isDef() && mop.isUse();
           
       for (unsigned p=0; p < i; ++p) {
         SchedGraphNode* prevNode = regRefVec[p].first;
@@ -351,8 +351,8 @@
           unsigned int prevOpNum = regRefVec[p].second;
           const MachineOperand& prevMop =
             prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
-          bool prevIsDef = prevMop.opIsDefOnly();
-          bool prevIsDefAndUse = prevMop.opIsDefAndUse();
+          bool prevIsDef = prevMop.isDef() && !prevMop.isUse();
+          bool prevIsDefAndUse = prevMop.isDef() && prevMop.isUse();
           if (isDef) {
             if (prevIsDef)
               new SchedGraphEdge(prevNode, node, regNum,
@@ -381,10 +381,8 @@
 				  const RefVec& defVec,
 				  const Value* defValue,
 				  bool  refNodeIsDef,
-				  bool  refNodeIsDefAndUse,
+				  bool  refNodeIsUse,
 				  const TargetMachine& target) {
-  bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
-  
   // Add true or output dep edges from all def nodes before refNode in BB.
   // Add anti or output dep edges to all def nodes after refNode.
   for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
@@ -393,7 +391,7 @@
     
     if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
       // (*).first is before refNode
-      if (refNodeIsDef)
+      if (refNodeIsDef && !refNodeIsUse)
         (void) new SchedGraphEdge((*I).first, refNode, defValue,
                                   SchedGraphEdge::OutputDep);
       if (refNodeIsUse)
@@ -401,7 +399,7 @@
                                   SchedGraphEdge::TrueDep);
     } else {
       // (*).first is after refNode
-      if (refNodeIsDef)
+      if (refNodeIsDef && !refNodeIsUse)
         (void) new SchedGraphEdge(refNode, (*I).first, defValue,
                                   SchedGraphEdge::OutputDep);
       if (refNodeIsUse)
@@ -429,8 +427,8 @@
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
           addEdgesForValue(node, I->second, srcI,
-                           MI.getOperand(i).opIsDefOnly(),
-                           MI.getOperand(i).opIsDefAndUse(), target);
+                           MI.getOperand(i).isDef(), MI.getOperand(i).isUse(),
+                           target);
       }
       break;
       
@@ -454,13 +452,13 @@
   // value of a Ret instruction.
   // 
   for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
-    if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
+    if (MI.getImplicitOp(i).isUse())
       if (const Value* srcI = MI.getImplicitRef(i)) {
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
           addEdgesForValue(node, I->second, srcI,
-                           MI.getImplicitOp(i).opIsDefOnly(),
-                           MI.getImplicitOp(i).opIsDefAndUse(), target);
+                           MI.getImplicitOp(i).isDef(),
+                           MI.getImplicitOp(i).isUse(), target);
       }
 }
 
@@ -512,8 +510,7 @@
     }
     
     // ignore all other non-def operands
-    if (!MI.getOperand(i).opIsDefOnly() &&
-        !MI.getOperand(i).opIsDefAndUse())
+    if (!MI.getOperand(i).isDef())
       continue;
       
     // We must be defining a value.
@@ -539,10 +536,10 @@
       continue;                     // nothing more to do
     }
 
-    if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+    if (mop.isDef()) {
       assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
-      valueToDefVecMap[MI.getImplicitRef(i)].push_back(std::make_pair(node,
-                                                                          -i)); 
+      valueToDefVecMap[MI.getImplicitRef(i)].push_back(
+        std::make_pair(node, -i)); 
     }
   }
 }
diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
index 73e5480..a58aed9 100644
--- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
@@ -178,8 +178,8 @@
 
         // Bit-selection flags indicate an instruction that is extracting
         // bits from its operand so ignore this even if it is a big constant.
-        if (mop.opHiBits32() || mop.opLoBits32() ||
-            mop.opHiBits64() || mop.opLoBits64())
+        if (mop.isHiBits32() || mop.isLoBits32() ||
+            mop.isHiBits64() || mop.isLoBits64())
           continue;
 
         opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 52cf73b..2850858 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -293,7 +293,7 @@
                 if (!mop.isRegister())
                     continue;
 
-                if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+                if (mop.isDef()) {
                     unsigned reg = mop.getAllocatedRegNum();
                     if (reg < MRegisterInfo::FirstVirtualRegister)
                         handlePhysicalRegisterDef(mbb, mi, reg);
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 358d5d0..a622b05 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -226,7 +226,7 @@
       // Process all explicit uses...
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
 	MachineOperand &MO = MI->getOperand(i);
-	if (MO.opIsUse() || MO.opIsDefAndUse()) {
+	if (MO.isUse()) {
 	  if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
 	    HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
 	  } else if (MO.isPhysicalRegister() && 
@@ -244,7 +244,7 @@
       // Process all explicit defs...
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
 	MachineOperand &MO = MI->getOperand(i);
-	if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
+	if (MO.isDef()) {
 	  if (MO.isVirtualRegister()) {
 	    VarInfo &VRInfo = getVarInfo(MO.getReg());
 
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index ef31cc4..9d7b1b2 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -153,8 +153,8 @@
   for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
     if (*O == oldVal)
       if (!defsOnly ||
-          notDefsAndUses && O.isDefOnly() ||
-          !notDefsAndUses && !O.isUseOnly())
+          notDefsAndUses && (O.isDef() && !O.isUse()) ||
+          !notDefsAndUses && O.isDef())
         {
           O.getMachineOperand().value = newVal;
           ++numSubst;
@@ -166,8 +166,8 @@
   for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
     if (getImplicitRef(i) == oldVal)
       if (!defsOnly ||
-          notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
-          !notDefsAndUses && !getImplicitOp(i).opIsUse())
+          notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
+          !notDefsAndUses && getImplicitOp(i).isDef())
         {
           getImplicitOp(i).value = newVal;
           ++numSubst;
@@ -210,13 +210,13 @@
                   const TargetMachine &TM) {
   const MRegisterInfo *MRI = TM.getRegisterInfo();
   bool CloseParen = true;
-  if (MO.opHiBits32())
+  if (MO.isHiBits32())
     OS << "%lm(";
-  else if (MO.opLoBits32())
+  else if (MO.isLoBits32())
     OS << "%lo(";
-  else if (MO.opHiBits64())
+  else if (MO.isHiBits64())
     OS << "%hh(";
-  else if (MO.opLoBits64())
+  else if (MO.isLoBits64())
     OS << "%hm(";
   else
     CloseParen = false;
@@ -289,8 +289,7 @@
   unsigned StartOp = 0;
 
    // Specialize printing if op#0 is definition
-  if (getNumOperands() &&
-      (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
+  if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
       llvm::print(getOperand(0), OS, TM);
     OS << " = ";
     ++StartOp;   // Don't print this operand again!
@@ -304,10 +303,11 @@
     OS << " ";
     llvm::print(mop, OS, TM);
     
-    if (mop.opIsDefAndUse())
-      OS << "<def&use>";
-    else if (mop.opIsDefOnly())
-      OS << "<def>";
+    if (mop.isDef())
+      if (mop.isUse())
+        OS << "<def&use>";
+      else
+        OS << "<def>";
   }
     
   // code for printing implicit references
@@ -316,10 +316,11 @@
     for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
       OS << "\t";
       OutputValue(OS, getImplicitRef(i));
-      if (getImplicitOp(i).opIsDefAndUse())
-        OS << "<def&use>";
-      else if (getImplicitOp(i).opIsDefOnly())
-        OS << "<def>";
+      if (getImplicitOp(i).isDef())
+          if (getImplicitOp(i).isUse())
+            OS << "<def&use>";
+          else
+            OS << "<def>";
     }
   }
   
@@ -333,10 +334,11 @@
   
   for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
     os << "\t" << MI.getOperand(i);
-    if (MI.getOperand(i).opIsDefOnly())
-      os << "<d>";
-    if (MI.getOperand(i).opIsDefAndUse())
-      os << "<d&u>";
+    if (MI.getOperand(i).isDef())
+      if (MI.getOperand(i).isUse())
+        os << "<d&u>";
+      else
+        os << "<d>";
   }
   
   // code for printing implicit references
@@ -345,8 +347,11 @@
     os << "\tImplicit: ";
     for (unsigned z=0; z < NumOfImpRefs; z++) {
       OutputValue(os, MI.getImplicitRef(z)); 
-      if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
-      if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
+      if (MI.getImplicitOp(z).isDef())
+          if (MI.getImplicitOp(z).isUse())
+            os << "<d&u>";
+          else
+            os << "<d>";
       os << "\t";
     }
   }
@@ -356,13 +361,13 @@
 
 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
 {
-  if (MO.opHiBits32())
+  if (MO.isHiBits32())
     OS << "%lm(";
-  else if (MO.opLoBits32())
+  else if (MO.isLoBits32())
     OS << "%lo(";
-  else if (MO.opHiBits64())
+  else if (MO.isHiBits64())
     OS << "%hh(";
-  else if (MO.opLoBits64())
+  else if (MO.isLoBits64())
     OS << "%hm(";
   
   switch (MO.getType())
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index c4b811a..4d34080 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -175,7 +175,7 @@
         for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
           MachineOperand &MO = PrevInst->getOperand(i);
           if (MO.isVirtualRegister() && MO.getReg() == IncomingReg)
-            if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
+            if (MO.isDef()) {
               HaveNotEmitted = false;
               break;
             }             
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 8fc9b5b..bb5ad47 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -118,8 +118,7 @@
 	  MachineOperand &MO = (*I)->getOperand(i);
 	  assert(!MO.isVirtualRegister() &&
 		 "Register allocation must be performed!");
-	  if (MO.isPhysicalRegister() &&
-	      (MO.opIsDefOnly() || MO.opIsDefAndUse()))
+	  if (MO.isPhysicalRegister() && MO.isDef())
 	    ModifiedRegs[MO.getReg()] = true;         // Register is modified
 	}
 	++I;
diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
index 9fd04d2..3806804 100644
--- a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
@@ -184,7 +184,7 @@
       // for each operand that is defined by the instruction
       for (MachineInstr::val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI)
-	if (OpI.isDefOnly() || OpI.isDefAndUse()) {     
+	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
           bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
@@ -203,8 +203,7 @@
       // iterate over implicit MI operands and create a new LR
       // for each operand that is defined by the instruction
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
-	if (MInst->getImplicitOp(i).opIsDefOnly() ||
-            MInst->getImplicitOp(i).opIsDefAndUse()) {     
+	if (MInst->getImplicitOp(i).isDef()) {
 	  const Value *Def = MInst->getImplicitRef(i);
           LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
 
@@ -342,7 +341,7 @@
       // iterate over  MI operands to find defs
       for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
             DefE = MI->end(); DefI != DefE; ++DefI) {
-	if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified
+	if (DefI.isDef()) { // this operand is modified
 	  LiveRange *LROfDef = getLiveRangeForValue( *DefI );
 	  RegClass *RCOfDef = LROfDef->getRegClass();
 
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 332ae95..a9a5f3d 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -250,7 +250,7 @@
       // iterate over all MI operands to find defs
       for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI) {
-       	if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
+       	if (OpI.isDef()) // create a new LR since def
 	  addInterference(*OpI, &LVSetAI, isCallInst);
 
 	// Calculate the spill cost of each live range
@@ -269,8 +269,7 @@
       // instr (currently, only calls have this).
       unsigned NumOfImpRefs =  MInst->getNumImplicitRefs();
       for (unsigned z=0; z < NumOfImpRefs; z++) 
-        if (MInst->getImplicitOp(z).opIsDefOnly() ||
-	    MInst->getImplicitOp(z).opIsDefAndUse())
+        if (MInst->getImplicitOp(z).isDef())
 	  addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
 
     } // for all machine instructions in BB
@@ -295,7 +294,7 @@
   for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
          ItE = MInst->end(); It1 != ItE; ++It1) {
     const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1); 
-    assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
+    assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
 
     MachineInstr::const_val_op_iterator It2 = It1;
     for (++It2; It2 != ItE; ++It2) {
@@ -645,8 +644,8 @@
 	 "Return value of a ret must be handled elsewhere");
 
   MachineOperand& Op = MInst->getOperand(OpNum);
-  bool isDef =  Op.opIsDefOnly();
-  bool isDefAndUse = Op.opIsDefAndUse();
+  bool isDef =  Op.isDef();
+  bool isUse = Op.isUse();
   unsigned RegType = MRI.getRegTypeForLR(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
@@ -699,7 +698,7 @@
       assert(scratchReg != MRI.getInvalidRegNum());
     }
   
-  if (!isDef || isDefAndUse) {
+  if (isUse) {
     // for a USE, we have to load the value of LR from stack to a TmpReg
     // and use the TmpReg as one operand of instruction
     
@@ -712,7 +711,7 @@
     AdIMid.clear();
   }
   
-  if (isDef || isDefAndUse) {   // if this is a Def
+  if (isDef) {   // if this is a Def
     // for a DEF, we have to store the value produced by this instruction
     // on the stack position allocated for this LR
     
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index dd94ad3..9e8089a 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -213,7 +213,7 @@
                      ii = mbb->begin(), ie = mbb->end();
                  ii != ie; ++ii) {
                 MachineInstr* instr = *ii;
-                     
+
                 std::cerr << i++ << "\t";
                 instr->print(std::cerr, *tm_);
             }
@@ -245,7 +245,6 @@
 
         DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
         DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end()));
-
         processActiveIntervals(i);
         // processInactiveIntervals(i);
 
@@ -281,7 +280,7 @@
         }
         // remove interval from active
     }
-    
+
     DEBUG(std::cerr << "finished register allocation\n");
     DEBUG(printVirt2PhysMap());
 
@@ -322,7 +321,7 @@
             for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
                  i != e; ++i) {
                 MachineOperand& op = (*currentInstr_)->getOperand(i);
-                if (op.isVirtualRegister() && op.opIsUse()) {
+                if (op.isVirtualRegister() && op.isUse()) {
                     unsigned virtReg = op.getAllocatedRegNum();
                     unsigned physReg = v2pMap_[virtReg];
                     if (!physReg) {
@@ -345,13 +344,13 @@
             for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
                  i != e; ++i) {
                 MachineOperand& op = (*currentInstr_)->getOperand(i);
-                if (op.isVirtualRegister() && !op.opIsUse()) {
+                if (op.isVirtualRegister() && op.isDef()) {
                     unsigned virtReg = op.getAllocatedRegNum();
                     unsigned physReg = v2pMap_[virtReg];
                     if (!physReg) {
                         physReg = getFreeTempPhysReg(virtReg);
                     }
-                    if (op.opIsDefAndUse()) {
+                    if (op.isUse()) { // def and use
                         loadVirt2PhysReg(virtReg, physReg);
                     }
                     else {
@@ -373,7 +372,7 @@
                 (*currentInstr_)->getOperand(1).getAllocatedRegNum()) {
                 assert((*currentInstr_)->getOperand(1).isRegister() &&
                        (*currentInstr_)->getOperand(1).getAllocatedRegNum() &&
-                       (*currentInstr_)->getOperand(1).opIsUse() &&
+                       (*currentInstr_)->getOperand(1).isUse() &&
                        "Two address instruction invalid");
 
                 unsigned regA =
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 4a3eb11..425c9d4 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -507,7 +507,9 @@
     // to be live-in, or the input is badly hosed.
     //
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
-      if (MI->getOperand(i).opIsUse() && MI->getOperand(i).isVirtualRegister()){
+      if (MI->getOperand(i).isUse() &&
+          !MI->getOperand(i).isDef() &&
+          MI->getOperand(i).isVirtualRegister()){
         unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
         unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
         MI->SetMachineOperandReg(i, PhysSrcReg);  // Assign the input register
@@ -541,8 +543,7 @@
     // Loop over all of the operands of the instruction, spilling registers that
     // are defined, and marking explicit destinations in the PhysRegsUsed map.
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
-      if ((MI->getOperand(i).opIsDefOnly() ||
-           MI->getOperand(i).opIsDefAndUse()) &&
+      if (MI->getOperand(i).isDef() &&
           MI->getOperand(i).isPhysicalRegister()) {
         unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
         spillPhysReg(MBB, I, Reg, true);  // Spill any existing value in the reg
@@ -565,8 +566,8 @@
     // we need to scavenge a register.
     //
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
-      if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse())
-          && MI->getOperand(i).isVirtualRegister()) {
+      if (MI->getOperand(i).isDef() &&
+          MI->getOperand(i).isVirtualRegister()) {
         unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
         unsigned DestPhysReg;
 
@@ -585,7 +586,7 @@
           // This maps a = b + c into b += c, and saves b into a's spot
           assert(MI->getOperand(1).isPhysicalRegister()  &&
                  MI->getOperand(1).getAllocatedRegNum() &&
-                 MI->getOperand(1).opIsUse() &&
+                 MI->getOperand(1).isUse() &&
                  "Two address instruction invalid!");
           DestPhysReg = MI->getOperand(1).getAllocatedRegNum();
 
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 202123a..44f37c6 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -184,13 +184,13 @@
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
-          if (op.opIsDefOnly() || op.opIsDefAndUse()) {
+          if (op.isDef()) {
             if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
               // must be same register number as the first operand
               // This maps a = b + c into b += c, and saves b into a's spot
               assert(MI->getOperand(1).isRegister()  &&
                      MI->getOperand(1).getAllocatedRegNum() &&
-                     MI->getOperand(1).opIsUse() &&
+                     MI->getOperand(1).isUse() &&
                      "Two address instruction invalid!");
 
               physReg = MI->getOperand(1).getAllocatedRegNum();
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 3a80880..2dafe62 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -342,8 +342,8 @@
       unsigned int opNum   = regRefVec[i].second;
       const MachineOperand& mop =
         node->getMachineInstr()->getExplOrImplOperand(opNum);
-      bool isDef = mop.opIsDefOnly();
-      bool isDefAndUse = mop.opIsDefAndUse();
+      bool isDef = mop.isDef() && !mop.isUse();
+      bool isDefAndUse = mop.isDef() && mop.isUse();
           
       for (unsigned p=0; p < i; ++p) {
         SchedGraphNode* prevNode = regRefVec[p].first;
@@ -351,8 +351,8 @@
           unsigned int prevOpNum = regRefVec[p].second;
           const MachineOperand& prevMop =
             prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
-          bool prevIsDef = prevMop.opIsDefOnly();
-          bool prevIsDefAndUse = prevMop.opIsDefAndUse();
+          bool prevIsDef = prevMop.isDef() && !prevMop.isUse();
+          bool prevIsDefAndUse = prevMop.isDef() && prevMop.isUse();
           if (isDef) {
             if (prevIsDef)
               new SchedGraphEdge(prevNode, node, regNum,
@@ -381,10 +381,8 @@
 				  const RefVec& defVec,
 				  const Value* defValue,
 				  bool  refNodeIsDef,
-				  bool  refNodeIsDefAndUse,
+				  bool  refNodeIsUse,
 				  const TargetMachine& target) {
-  bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
-  
   // Add true or output dep edges from all def nodes before refNode in BB.
   // Add anti or output dep edges to all def nodes after refNode.
   for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
@@ -393,7 +391,7 @@
     
     if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
       // (*).first is before refNode
-      if (refNodeIsDef)
+      if (refNodeIsDef && !refNodeIsUse)
         (void) new SchedGraphEdge((*I).first, refNode, defValue,
                                   SchedGraphEdge::OutputDep);
       if (refNodeIsUse)
@@ -401,7 +399,7 @@
                                   SchedGraphEdge::TrueDep);
     } else {
       // (*).first is after refNode
-      if (refNodeIsDef)
+      if (refNodeIsDef && !refNodeIsUse)
         (void) new SchedGraphEdge(refNode, (*I).first, defValue,
                                   SchedGraphEdge::OutputDep);
       if (refNodeIsUse)
@@ -429,8 +427,8 @@
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
           addEdgesForValue(node, I->second, srcI,
-                           MI.getOperand(i).opIsDefOnly(),
-                           MI.getOperand(i).opIsDefAndUse(), target);
+                           MI.getOperand(i).isDef(), MI.getOperand(i).isUse(),
+                           target);
       }
       break;
       
@@ -454,13 +452,13 @@
   // value of a Ret instruction.
   // 
   for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
-    if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
+    if (MI.getImplicitOp(i).isUse())
       if (const Value* srcI = MI.getImplicitRef(i)) {
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
           addEdgesForValue(node, I->second, srcI,
-                           MI.getImplicitOp(i).opIsDefOnly(),
-                           MI.getImplicitOp(i).opIsDefAndUse(), target);
+                           MI.getImplicitOp(i).isDef(),
+                           MI.getImplicitOp(i).isUse(), target);
       }
 }
 
@@ -512,8 +510,7 @@
     }
     
     // ignore all other non-def operands
-    if (!MI.getOperand(i).opIsDefOnly() &&
-        !MI.getOperand(i).opIsDefAndUse())
+    if (!MI.getOperand(i).isDef())
       continue;
       
     // We must be defining a value.
@@ -539,10 +536,10 @@
       continue;                     // nothing more to do
     }
 
-    if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+    if (mop.isDef()) {
       assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
-      valueToDefVecMap[MI.getImplicitRef(i)].push_back(std::make_pair(node,
-                                                                          -i)); 
+      valueToDefVecMap[MI.getImplicitRef(i)].push_back(
+        std::make_pair(node, -i)); 
     }
   }
 }
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index 73e5480..a58aed9 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -178,8 +178,8 @@
 
         // Bit-selection flags indicate an instruction that is extracting
         // bits from its operand so ignore this even if it is a big constant.
-        if (mop.opHiBits32() || mop.opLoBits32() ||
-            mop.opHiBits64() || mop.opLoBits64())
+        if (mop.isHiBits32() || mop.isLoBits32() ||
+            mop.isHiBits64() || mop.isLoBits64())
           continue;
 
         opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
index 758f1b1..270fbbd 100644
--- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
+++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
@@ -52,12 +52,12 @@
     // iterate over  MI operands to find defs
     for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end();
          OpI != OpE; ++OpI)
-      if (OpI.isDefOnly() || OpI.isDefAndUse()) // add to Defs if this operand is a def
+      if (OpI.isDef()) // add to Defs if this operand is a def
 	addDef(*OpI);
 
     // do for implicit operands as well
     for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i)
-      if (MI->getImplicitOp(i).opIsDefOnly() || MI->getImplicitOp(i).opIsDefAndUse())
+      if (MI->getImplicitOp(i).isDef())
 	addDef(MI->getImplicitRef(i));
     
     // iterate over MI operands to find uses
@@ -68,8 +68,7 @@
       if (isa<BasicBlock>(Op))
 	continue;             // don't process labels
 
-      if (OpI.isUseOnly() || OpI.isDefAndUse()) {
-                                // add to Uses only if this operand is a use
+      if (OpI.isUse()) { // add to Uses only if this operand is a use
         //
         // *** WARNING: The following code for handling dummy PHI machine
         //     instructions is untested.  The previous code was broken and I
@@ -104,7 +103,7 @@
       if (Op->getType() == Type::LabelTy)             // don't process labels
 	continue;
 
-      if (MI->getImplicitOp(i).opIsUse() || MI->getImplicitOp(i).opIsDefAndUse())
+      if (MI->getImplicitOp(i).isUse())
 	addUse(Op);
     }
   } // for all machine instructions
diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
index 8f0e318..e342760 100644
--- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
+++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
@@ -235,14 +235,13 @@
 static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
   for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
          OpE = MInst->end(); OpI != OpE; ++OpI) {
-    if (OpI.isDefOnly() || OpI.isDefAndUse()) // kill if this operand is a def
+    if (OpI.isDef())                          // kill if this operand is a def
       LVS.erase(*OpI);                        // this definition kills any uses
   }
 
   // do for implicit operands as well
   for (unsigned i=0; i < MInst->getNumImplicitRefs(); ++i) {
-    if (MInst->getImplicitOp(i).opIsDefOnly() ||
-        MInst->getImplicitOp(i).opIsDefAndUse())
+    if (MInst->getImplicitOp(i).isDef())
       LVS.erase(MInst->getImplicitRef(i));
   }
 
@@ -250,14 +249,13 @@
          OpE = MInst->end(); OpI != OpE; ++OpI) {
     if (!isa<BasicBlock>(*OpI))      // don't process labels
       // add only if this operand is a use
-      if (!OpI.isDefOnly() || OpI.isDefAndUse() )
+      if (OpI.isUse())
         LVS.insert(*OpI);            // An operand is a use - so add to use set
   }
 
   // do for implicit operands as well
   for (unsigned i = 0, e = MInst->getNumImplicitRefs(); i != e; ++i)
-    if (MInst->getImplicitOp(i).opIsUse() ||
-        MInst->getImplicitOp(i).opIsDefAndUse())
+    if (MInst->getImplicitOp(i).isUse())
       LVS.insert(MInst->getImplicitRef(i));
 }
 
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index 9fd04d2..3806804 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -184,7 +184,7 @@
       // for each operand that is defined by the instruction
       for (MachineInstr::val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI)
-	if (OpI.isDefOnly() || OpI.isDefAndUse()) {     
+	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
           bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
@@ -203,8 +203,7 @@
       // iterate over implicit MI operands and create a new LR
       // for each operand that is defined by the instruction
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
-	if (MInst->getImplicitOp(i).opIsDefOnly() ||
-            MInst->getImplicitOp(i).opIsDefAndUse()) {     
+	if (MInst->getImplicitOp(i).isDef()) {
 	  const Value *Def = MInst->getImplicitRef(i);
           LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
 
@@ -342,7 +341,7 @@
       // iterate over  MI operands to find defs
       for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
             DefE = MI->end(); DefI != DefE; ++DefI) {
-	if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified
+	if (DefI.isDef()) { // this operand is modified
 	  LiveRange *LROfDef = getLiveRangeForValue( *DefI );
 	  RegClass *RCOfDef = LROfDef->getRegClass();
 
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 332ae95..a9a5f3d 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -250,7 +250,7 @@
       // iterate over all MI operands to find defs
       for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI) {
-       	if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
+       	if (OpI.isDef()) // create a new LR since def
 	  addInterference(*OpI, &LVSetAI, isCallInst);
 
 	// Calculate the spill cost of each live range
@@ -269,8 +269,7 @@
       // instr (currently, only calls have this).
       unsigned NumOfImpRefs =  MInst->getNumImplicitRefs();
       for (unsigned z=0; z < NumOfImpRefs; z++) 
-        if (MInst->getImplicitOp(z).opIsDefOnly() ||
-	    MInst->getImplicitOp(z).opIsDefAndUse())
+        if (MInst->getImplicitOp(z).isDef())
 	  addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
 
     } // for all machine instructions in BB
@@ -295,7 +294,7 @@
   for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
          ItE = MInst->end(); It1 != ItE; ++It1) {
     const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1); 
-    assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
+    assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
 
     MachineInstr::const_val_op_iterator It2 = It1;
     for (++It2; It2 != ItE; ++It2) {
@@ -645,8 +644,8 @@
 	 "Return value of a ret must be handled elsewhere");
 
   MachineOperand& Op = MInst->getOperand(OpNum);
-  bool isDef =  Op.opIsDefOnly();
-  bool isDefAndUse = Op.opIsDefAndUse();
+  bool isDef =  Op.isDef();
+  bool isUse = Op.isUse();
   unsigned RegType = MRI.getRegTypeForLR(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
@@ -699,7 +698,7 @@
       assert(scratchReg != MRI.getInvalidRegNum());
     }
   
-  if (!isDef || isDefAndUse) {
+  if (isUse) {
     // for a USE, we have to load the value of LR from stack to a TmpReg
     // and use the TmpReg as one operand of instruction
     
@@ -712,7 +711,7 @@
     AdIMid.clear();
   }
   
-  if (isDef || isDefAndUse) {   // if this is a Def
+  if (isDef) {   // if this is a Def
     // for a DEF, we have to store the value produced by this instruction
     // on the stack position allocated for this LR
     
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 1e75aca..ec190ca 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -735,13 +735,13 @@
 {
   bool needBitsFlag = true;
   
-  if (mop.opHiBits32())
+  if (mop.isHiBits32())
     toAsm << "%lm(";
-  else if (mop.opLoBits32())
+  else if (mop.isLoBits32())
     toAsm << "%lo(";
-  else if (mop.opHiBits64())
+  else if (mop.isHiBits64())
     toAsm << "%hh(";
-  else if (mop.opLoBits64())
+  else if (mop.isLoBits64())
     toAsm << "%hm(";
   else
     needBitsFlag = false;
diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index be677e0..9a51faa 100644
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -699,13 +699,13 @@
   // are used in SPARC assembly. (Some of these make no sense in combination
   // with some of the above; we'll trust that the instruction selector
   // will not produce nonsense, and not check for valid combinations here.)
-  if (MO.opLoBits32()) {          // %lo(val) == %lo() in Sparc ABI doc
+  if (MO.isLoBits32()) {          // %lo(val) == %lo() in Sparc ABI doc
     return rv & 0x03ff;
-  } else if (MO.opHiBits32()) {   // %lm(val) == %hi() in Sparc ABI doc
+  } else if (MO.isHiBits32()) {   // %lm(val) == %hi() in Sparc ABI doc
     return (rv >> 10) & 0x03fffff;
-  } else if (MO.opLoBits64()) {   // %hm(val) == %ulo() in Sparc ABI doc
+  } else if (MO.isLoBits64()) {   // %hm(val) == %ulo() in Sparc ABI doc
     return (rv >> 32) & 0x03ff;
-  } else if (MO.opHiBits64()) {   // %hh(val) == %uhi() in Sparc ABI doc
+  } else if (MO.isHiBits64()) {   // %hh(val) == %uhi() in Sparc ABI doc
     return rv >> 42;
   } else {                        // (unadorned) val
     return rv;
@@ -747,10 +747,10 @@
         int64_t branchTarget = (Location - (long)Ref) >> 2;
         // Save the flags.
         bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;   
-        if (op.opLoBits32()) { loBits32=true; }
-        if (op.opHiBits32()) { hiBits32=true; }
-        if (op.opLoBits64()) { loBits64=true; }
-        if (op.opHiBits64()) { hiBits64=true; }
+        if (op.isLoBits32()) { loBits32=true; }
+        if (op.isHiBits32()) { hiBits32=true; }
+        if (op.isLoBits64()) { loBits64=true; }
+        if (op.isHiBits64()) { hiBits64=true; }
         MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
                                    branchTarget);
         if (loBits32) { MI->setOperandLo32(ii); }
diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index 4c887e1..89008ae 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -174,7 +174,7 @@
           MachineInstr *MI = *I;
           for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
             MachineOperand &MO = MI->getOperand(i);
-            if (MO.isVirtualRegister() && MO.opIsDefOnly())
+            if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
               setDefinition(MO.getReg(), MI);
           }
         }
@@ -233,7 +233,7 @@
     /// register, return the machine instruction defining it, otherwise, return
     /// null.
     MachineInstr *getDefiningInst(MachineOperand &MO) {
-      if (!MO.opIsUse() || !MO.isVirtualRegister()) return 0;
+      if (MO.isDef() || !MO.isVirtualRegister()) return 0;
       return UDC->getDefinition(MO.getReg());
     }
 
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index 289a68b..4d586c0 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -551,8 +551,7 @@
       }
     } else {
       unsigned i = 0;
-      if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() || 
-                                   MI->getOperand(0).opIsDefAndUse())) {
+      if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
 	printOp(MI->getOperand(0));
 	O << " = ";
 	++i;
@@ -561,11 +560,9 @@
 
       for (unsigned e = MI->getNumOperands(); i != e; ++i) {
 	O << " ";
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
 	printOp(MI->getOperand(i));
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
       }
     }
     O << "\n";
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index 289a68b..4d586c0 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -551,8 +551,7 @@
       }
     } else {
       unsigned i = 0;
-      if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() || 
-                                   MI->getOperand(0).opIsDefAndUse())) {
+      if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
 	printOp(MI->getOperand(0));
 	O << " = ";
 	++i;
@@ -561,11 +560,9 @@
 
       for (unsigned e = MI->getNumOperands(); i != e; ++i) {
 	O << " ";
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
 	printOp(MI->getOperand(i));
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
       }
     }
     O << "\n";
diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index 4c887e1..89008ae 100644
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -174,7 +174,7 @@
           MachineInstr *MI = *I;
           for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
             MachineOperand &MO = MI->getOperand(i);
-            if (MO.isVirtualRegister() && MO.opIsDefOnly())
+            if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
               setDefinition(MO.getReg(), MI);
           }
         }
@@ -233,7 +233,7 @@
     /// register, return the machine instruction defining it, otherwise, return
     /// null.
     MachineInstr *getDefiningInst(MachineOperand &MO) {
-      if (!MO.opIsUse() || !MO.isVirtualRegister()) return 0;
+      if (MO.isDef() || !MO.isVirtualRegister()) return 0;
       return UDC->getDefinition(MO.getReg());
     }