Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index e51699b..2bf7e51 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index f436e97..d43a76e 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -257,10 +257,10 @@
else if (MO.isMBB())
emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
else {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "ERROR: Unknown type of MachineOperand: " << MO;
- llvm_report_error(Msg.str());
+#ifndef NDEBUG
+ cerr << MO;
+#endif
+ llvm_unreachable();
}
return 0;
}
@@ -588,7 +588,7 @@
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
- llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
+ LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
@@ -1119,8 +1119,9 @@
void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
- if (TID.Opcode == ARM::TPsoft)
- llvm_report_error("ARM::TPsoft FIXME"); // FIXME
+ if (TID.Opcode == ARM::TPsoft) {
+ LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME
+ }
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 6d7e41c..71a6305 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -30,6 +30,9 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
using namespace llvm;
static const unsigned arm_dsubreg_0 = 5;
diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp
index bc28919..c9e04c9 100644
--- a/lib/Target/ARM/ARMJITInfo.cpp
+++ b/lib/Target/ARM/ARMJITInfo.cpp
@@ -123,12 +123,12 @@
// ldr pc, [pc,#-4]
// <addr>
if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
- llvm_report_error("ERROR: Unable to mark stub writable");
+ LLVM_UNREACHABLE("ERROR: Unable to mark stub writable");
}
*(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
*(intptr_t *)(StubAddr+4) = NewVal;
if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
- llvm_report_error("ERROR: Unable to mark stub executable");
+ LLVM_UNREACHABLE("ERROR: Unable to mark stub executable");
}
}
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index d9e21b8..67c4258 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -120,7 +120,7 @@
case ARM::FSTD:
NumFSTMGened++;
return ARM::FSTMD;
- default: llvm_report_error("Unhandled opcode!");
+ default: LLVM_UNREACHABLE("Unhandled opcode!");
}
return 0;
}
@@ -442,7 +442,7 @@
case ARM::FLDD: return ARM::FLDMD;
case ARM::FSTS: return ARM::FSTMS;
case ARM::FSTD: return ARM::FSTMD;
- default: llvm_report_error("Unhandled opcode!");
+ default: LLVM_UNREACHABLE("Unhandled opcode!");
}
return 0;
}
@@ -455,7 +455,7 @@
case ARM::FLDD: return ARM::FLDMD;
case ARM::FSTS: return ARM::FSTMS;
case ARM::FSTD: return ARM::FSTMD;
- default: llvm_report_error("Unhandled opcode!");
+ default: LLVM_UNREACHABLE("Unhandled opcode!");
}
return 0;
}
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 316f5ad..125b461 100644
--- a/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -32,6 +32,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
static cl::opt<bool>
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp
index bca205a..f5a8b82 100644
--- a/lib/Target/ARM/Thumb2RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp
@@ -455,8 +455,7 @@
break;
}
default:
- llvm_report_error("Unsupported addressing mode!");
- break;
+ LLVM_UNREACHABLE("Unsupported addressing mode!");
}
Offset += InstrOffs * Scale;