Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index 7f1673c..373a2ef 100644
--- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -36,6 +36,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetAsmInfo.h"
@@ -70,7 +71,7 @@
unsigned enumRegToMachineReg(unsigned enumReg) {
switch (enumReg) {
- default: assert(0 && "Unhandled register!"); break;
+ default: LLVM_UNREACHABLE("Unhandled register!");
case PPC::CR0: return 0;
case PPC::CR1: return 1;
case PPC::CR2: return 2;
@@ -80,7 +81,7 @@
case PPC::CR6: return 6;
case PPC::CR7: return 7;
}
- abort();
+ llvm_unreachable();
}
/// printInstruction - This method is automatically generated by tablegen
@@ -348,9 +349,7 @@
void PPCAsmPrinter::printOp(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Immediate:
- cerr << "printOp() does not handle immediate values\n";
- abort();
- return;
+ LLVM_UNREACHABLE("printOp() does not handle immediate values");
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMBB());
@@ -552,9 +551,7 @@
if (printInstruction(MI))
return; // Printer was automatically generated
- assert(0 && "Unhandled instruction in asm writer!");
- abort();
- return;
+ LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
}
/// runOnMachineFunction - This uses the printMachineInstruction()
@@ -709,8 +706,7 @@
case GlobalValue::PrivateLinkage:
break;
default:
- cerr << "Unknown linkage type!";
- abort();
+ LLVM_UNREACHABLE("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
@@ -940,8 +936,7 @@
case GlobalValue::PrivateLinkage:
break;
default:
- cerr << "Unknown linkage type!";
- abort();
+ LLVM_UNREACHABLE("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index eaa8269..c191f65 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -26,6 +26,8 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
@@ -263,8 +265,10 @@
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Reloc, MO.getMBB()));
} else {
+#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
- abort();
+#endif
+ llvm_unreachable();
}
return rv;
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 823e316..398a1fe 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -31,6 +31,8 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
@@ -600,8 +602,8 @@
case ISD::SETONE:
case ISD::SETOLE:
case ISD::SETOGE:
- assert(0 && "Should be lowered by legalize!");
- default: assert(0 && "Unknown condition!"); abort();
+ LLVM_UNREACHABLE("Should be lowered by legalize!");
+ default: LLVM_UNREACHABLE("Unknown condition!");
case ISD::SETOEQ:
case ISD::SETEQ: return PPC::PRED_EQ;
case ISD::SETUNE:
@@ -632,7 +634,7 @@
Invert = false;
Other = -1;
switch (CC) {
- default: assert(0 && "Unknown condition!"); abort();
+ default: LLVM_UNREACHABLE("Unknown condition!");
case ISD::SETOLT:
case ISD::SETLT: return 0; // Bit #0 = SETOLT
case ISD::SETOGT:
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 1c6b287..5b0c935 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -32,6 +32,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/DerivedTypes.h"
using namespace llvm;
@@ -2584,9 +2586,11 @@
}
if (Result) {
+#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString() << "\n";
- abort();
+#endif
+ llvm_unreachable();
}
}
} else {
@@ -4141,8 +4145,7 @@
}
return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
} else {
- assert(0 && "Unknown mul to lower!");
- abort();
+ LLVM_UNREACHABLE("Unknown mul to lower!");
}
}
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 87c612a..63adf32 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -20,6 +20,8 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetAsmInfo.h"
using namespace llvm;
@@ -485,8 +487,7 @@
.addReg(PPC::R0)
.addReg(PPC::R0));
} else {
- assert(0 && "Unknown regclass!");
- abort();
+ LLVM_UNREACHABLE("Unknown regclass!");
}
return false;
@@ -537,8 +538,7 @@
} else if (RC == PPC::VRRCRegisterClass) {
Opc = PPC::STVX;
} else {
- assert(0 && "Unknown regclass!");
- abort();
+ LLVM_UNREACHABLE("Unknown regclass!");
}
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, getKillRegState(isKill));
@@ -634,8 +634,7 @@
NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
.addReg(PPC::R0));
} else {
- assert(0 && "Unknown regclass!");
- abort();
+ LLVM_UNREACHABLE("Unknown regclass!");
}
}
@@ -677,8 +676,7 @@
} else if (RC == PPC::VRRCRegisterClass) {
Opc = PPC::LVX;
} else {
- assert(0 && "Unknown regclass!");
- abort();
+ LLVM_UNREACHABLE("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
index 7486d74..25f3785 100644
--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -18,6 +18,8 @@
#include "llvm/Function.h"
#include "llvm/System/Memory.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
@@ -197,8 +199,7 @@
);
#else
void PPC32CompilationCallback() {
- assert(0 && "This is not a power pc, you can't execute this!");
- abort();
+ LLVM_UNREACHABLE("This is not a power pc, you can't execute this!");
}
#endif
@@ -264,8 +265,7 @@
);
#else
void PPC64CompilationCallback() {
- assert(0 && "This is not a power pc, you can't execute this!");
- abort();
+ LLVM_UNREACHABLE("This is not a power pc, you can't execute this!");
}
#endif
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 97b1c57..26d08d0 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -37,7 +37,9 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
@@ -111,8 +113,7 @@
case R30: case X30: case F30: case V30: case CR7EQ: return 30;
case R31: case X31: case F31: case V31: case CR7UN: return 31;
default:
- cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
- abort();
+ LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
}
}