commit 4da27f66ca01a88277d8370617b2aebd5763ef3f
author Arnold Schwaighofer <arnold.schwaighofer@gmail.com> Mon Sep 22 14:50:07 2008 +0000
committer Arnold Schwaighofer <arnold.schwaighofer@gmail.com> Mon Sep 22 14:50:07 2008 +0000
tree 8c33aa2a19ad9ed57f4947b227592e2fdbbeffe0
parent c821c87af4285fb9f8dec3b1f0084b588ece00ba

Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56436 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86CallingConv.td

diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td
index e720b0b..b98b5d9 100644
--- a/lib/Target/X86/X86CallingConv.td
+++ b/lib/Target/X86/X86CallingConv.td
@@ -312,22 +312,6 @@
   CCDelegateTo<CC_X86_32_Common>
 ]>;
 
-/// Same as C calling convention except for non-free ECX which is used for storing 
-/// a potential pointer to the tail called function.
-def CC_X86_32_TailCall : CallingConv<[
-  // Promote i8/i16 arguments to i32.
-  CCIfType<[i8, i16], CCPromoteToType<i32>>,
-
-  // Nested function trampolines are currently not supported by fastcc.
-  
-  // The first 3 integer arguments, if marked 'inreg' and if the call is not
-  // a vararg call, are passed in integer registers.
-  CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>,
-
-  // Otherwise, same as everything else.
-  CCDelegateTo<CC_X86_32_Common>
-]>;
-
 def CC_X86_32_FastCall : CallingConv<[
   // Promote i8/i16 arguments to i32.
   CCIfType<[i8, i16], CCPromoteToType<i32>>,

lib/Target/X86/X86FastISel.cpp

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 3d27ff3..7747788 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -142,8 +142,6 @@
 
   if (CC == CallingConv::X86_FastCall)
     return CC_X86_32_FastCall;
-  else if (CC == CallingConv::Fast && isTaillCall)
-    return CC_X86_32_TailCall;
   else if (CC == CallingConv::Fast)
     return CC_X86_32_FastCC;
   else

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 3401a2c..78121bd 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -890,7 +890,7 @@
     SDValue TargetAddress = TailCall.getOperand(1);
     SDValue StackAdjustment = TailCall.getOperand(2);
     assert(((TargetAddress.getOpcode() == ISD::Register &&
-               (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
+               (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
                 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
               TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
               TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 
@@ -1098,8 +1098,6 @@
 
   if (CC == CallingConv::X86_FastCall)
     return CC_X86_32_FastCall;
-  else if (CC == CallingConv::Fast && PerformTailCallOpt)
-    return CC_X86_32_TailCall;
   else if (CC == CallingConv::Fast)
     return CC_X86_32_FastCC;
   else
@@ -1700,7 +1698,7 @@
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
     Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
   } else if (IsTailCall) {
-    unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
+    unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
 
     Chain = DAG.getCopyToReg(Chain, 
                              DAG.getRegister(Opc, getPointerTy()),