commit 4da632e6e09b96db4b3f9202cde4e6ca732001c1
author Craig Topper <craig.topper@gmail.com> Fri Sep 23 06:57:25 2011 +0000
committer Craig Topper <craig.topper@gmail.com> Fri Sep 23 06:57:25 2011 +0000
tree 2b2c73074cefca6d6e072e2615db00e10753fd93
parent aaa9fc2e375ac92c9ff0cff5265c79045affe8ba

Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/X86DisassemblerTables.cpp

diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index aed2727..b12660e 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -642,12 +642,16 @@
                                         InstructionContext  insnContext,
                                         uint8_t             opcode,
                                         const ModRMFilter   &filter,
-                                        InstrUID            uid) {
+                                        InstrUID            uid,
+                                        bool                is32bit) {
   unsigned index;
   
   ContextDecision &decision = *Tables[type];
 
   for (index = 0; index < IC_max; ++index) {
+    if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
+      continue;
+
     if (inheritsFrom((InstructionContext)index, 
                      InstructionSpecifiers[uid].insnContext))
       setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],