Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index ab40222..4118293 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -231,10 +231,15 @@
HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX
+ Is32Bit = false;
Is64Bit = false;
// FIXME: Is there some better way to check for In64BitMode?
std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
+ if (Predicates[i]->getName().find("32Bit") != Name.npos) {
+ Is32Bit = true;
+ break;
+ }
if (Predicates[i]->getName().find("64Bit") != Name.npos) {
Is64Bit = true;
break;
@@ -947,7 +952,7 @@
insnContext(),
currentOpcode,
*filter,
- UID);
+ UID, Is32Bit);
Spec->modifierType = MODIFIER_OPCODE;
Spec->modifierBase = opcodeToSet;
@@ -957,14 +962,14 @@
insnContext(),
opcodeToSet,
*filter,
- UID);
+ UID, Is32Bit);
}
} else {
tables.setTableFields(opcodeType,
insnContext(),
opcodeToSet,
*filter,
- UID);
+ UID, Is32Bit);
Spec->modifierType = MODIFIER_NONE;
Spec->modifierBase = opcodeToSet;