fix some 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 5ced8ef..ffbf186 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -359,7 +359,8 @@
Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
InFlag = Chain.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
+ Chain = CurDAG->getCopyToReg(Chain, IA64::B6,
+ targetEntryPoint, InFlag); // FLAG these?
InFlag = Chain.getValue(1);
CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
@@ -520,7 +521,8 @@
AddToISelQueue(Tmp);
Tmp =
SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
- CurDAG->getTargetConstant(1, MVT::i64),
+ CurDAG->getTargetConstant(1,
+ MVT::i64),
Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 6b75c3c..9cd9ef0 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -398,7 +398,7 @@
}
if(ValToConvert.getNode()) {
- Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
+ Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
}
}