add an initial cut at preinc loads for ppc32. This is broken for ppc64
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index a748238..3ad4bbc 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -26,8 +26,11 @@
#include "llvm/Intrinsics.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/Support/CommandLine.h"
using namespace llvm;
+static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc");
+
PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
@@ -861,29 +864,27 @@
SDOperand &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) {
- return false;
+ // Disabled by default for now.
+ if (!EnablePPCPreinc) return false;
-#if 0
- MVT::ValueType VT;
SDOperand Ptr;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- VT = LD->getLoadedVT();
-
- // TODO: handle other cases.
- if (VT != MVT::i32) return false;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
- Ptr = ST->getBasePtr();
- VT = ST->getStoredVT();
- // TODO: handle other cases.
+ ST = ST;
+ //Ptr = ST->getBasePtr();
+ //VT = ST->getStoredVT();
+ // TODO: handle stores.
return false;
} else
return false;
+ // TODO: Handle reg+reg.
+ if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
+ return false;
-
- return false;
-#endif
+ AM = ISD::PRE_INC;
+ return true;
}
//===----------------------------------------------------------------------===//