pre-RA-sched: Cleanup register pressure tracking.
Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133917 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index f03bf10..edd9e46 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -520,15 +520,7 @@
for (;DefIdx < NodeNumDefs; ++DefIdx) {
if (!Node->hasAnyUseOfValue(DefIdx))
continue;
- if (Node->isMachineOpcode() &&
- Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG &&
- Node->getOperand(0).getValueType() != MVT::untyped) {
- // Propagate the incoming (full-register) type. I doubt it's needed.
- ValueType = Node->getOperand(0).getValueType();
- }
- else {
- ValueType = Node->getValueType(DefIdx);
- }
+ ValueType = Node->getValueType(DefIdx);
++DefIdx;
return; // Found a normal regdef.
}