diff --git a/docs/CommandGuide/llc.pod b/docs/CommandGuide/llc.pod
index 910dfad..7b6eb05 100644
--- a/docs/CommandGuide/llc.pod
+++ b/docs/CommandGuide/llc.pod
@@ -46,11 +46,31 @@
 Overwrite output files. By default, B<llc> will refuse to overwrite
 an output file which already exists.
 
+=item B<-triple>=I<target triple>
+
+Override the target triple specified in the input bytecode file with the 
+specified string.
+
 =item B<-march>=I<arch>
 
 Specify the architecture for which to generate assembly, overriding the target
 encoded in the bytecode file.  See the output of B<llc --help> for a list of
-valid architectures.
+valid architectures.  By default this is inferred from the target triple or
+autodetected to the current architecture.
+
+=item B<-mcpu>=I<cpuname>
+
+Specify a specific chip in the current architecture to generate code for.
+By default this is inferred from the target triple and autodetected to 
+the current architecture.  For a list of available CPUs, use:
+B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
+
+=item B<-mattr>=I<a1,+a2,-a3,...>
+
+Override or control specific attributes of the target, such as whether SIMD
+operations are enabled or not.  The default set of attributes is set by the
+current CPU.  For a list of available attributes, use:
+B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
 
 =item B<--disable-fp-elim>
 
@@ -155,20 +175,6 @@
 
 =back
 
-=head2 SPARCV9-specific Options
-
-=over
-
-=item B<--disable-peephole>
-
-Disable peephole optimization pass.
-
-=item B<--disable-sched>
-
-Disable local scheduling pass.
-
-=back
-
 =head1 EXIT STATUS
 
 If B<llc> succeeds, it will exit with 0.  Otherwise, if an error occurs,
diff --git a/docs/CommandGuide/lli.pod b/docs/CommandGuide/lli.pod
index 25888c4..1bb3e9c 100644
--- a/docs/CommandGuide/lli.pod
+++ b/docs/CommandGuide/lli.pod
@@ -40,11 +40,32 @@
 Record the amount of time needed for each code-generation pass and print it to
 standard error.
 
+=item B<-triple>=I<target triple>
+
+Override the target triple specified in the input bytecode file with the 
+specified string.  This may result in a crash if you pick an
+architecture which is not compatible with the current system.
+
 =item B<-march>=I<arch>
 
-Use the specified non-default architecture arch when selecting a code generator
-for the just-in-time compiler. This may result in a crash if you pick an
-architecture which is not compatible with the hardware you are running B<lli> on.
+Specify the architecture for which to generate assembly, overriding the target
+encoded in the bytecode file.  See the output of B<llc --help> for a list of
+valid architectures.  By default this is inferred from the target triple or
+autodetected to the current architecture.
+
+=item B<-mcpu>=I<cpuname>
+
+Specify a specific chip in the current architecture to generate code for.
+By default this is inferred from the target triple and autodetected to 
+the current architecture.  For a list of available CPUs, use:
+B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
+
+=item B<-mattr>=I<a1,+a2,-a3,...>
+
+Override or control specific attributes of the target, such as whether SIMD
+operations are enabled or not.  The default set of attributes is set by the
+current CPU.  For a list of available attributes, use:
+B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
 
 =item B<-force-interpreter>=I<{false,true}>