More DCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index 52f55a8..f7a7eb5 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -163,12 +163,8 @@
///
enum Op {
ADDri,
- ADDrs,
- ADDrr,
MOVr,
- SUBri,
- SUBrs,
- SUBrr
+ SUBri
};
}
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index e5eb7bc..e186729 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -66,12 +66,8 @@
getOpcode(ARMII::Op Op) const {
switch (Op) {
case ARMII::ADDri: return ARM::ADDri;
- case ARMII::ADDrs: return ARM::ADDrs;
- case ARMII::ADDrr: return ARM::ADDrr;
case ARMII::MOVr: return ARM::MOVr;
case ARMII::SUBri: return ARM::SUBri;
- case ARMII::SUBrs: return ARM::SUBrs;
- case ARMII::SUBrr: return ARM::SUBrr;
default:
break;
}
diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp
index 43381a3..ed31132 100644
--- a/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -33,12 +33,8 @@
unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
switch (Op) {
case ARMII::ADDri: return ARM::tADDi8;
- case ARMII::ADDrs: return 0;
- case ARMII::ADDrr: return ARM::tADDrr;
case ARMII::MOVr: return ARM::tMOVr;
case ARMII::SUBri: return ARM::tSUBi8;
- case ARMII::SUBrs: return 0;
- case ARMII::SUBrr: return ARM::tSUBrr;
default:
break;
}
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index acb8232..ede8ab4 100644
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -34,12 +34,8 @@
unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
switch (Op) {
case ARMII::ADDri: return ARM::t2ADDri;
- case ARMII::ADDrs: return ARM::t2ADDrs;
- case ARMII::ADDrr: return ARM::t2ADDrr;
case ARMII::MOVr: return ARM::t2MOVr;
case ARMII::SUBri: return ARM::t2SUBri;
- case ARMII::SUBrs: return ARM::t2SUBrs;
- case ARMII::SUBrr: return ARM::t2SUBrr;
default:
break;
}