Add some very paranoid checking for operand/result reg class matchup
For instructions that define multiple results, use the right regclass
to define the result, not always the rc of result #0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23580 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 648db02..4d54d54 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -909,7 +909,7 @@
MI->addRegOperand(ResultReg, MachineOperand::Def);
for (unsigned i = 1; i != NumResults; ++i) {
assert(OpInfo[i].RegClass && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
+ MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
MachineOperand::Def);
}
return ResultReg;
@@ -951,8 +951,17 @@
assert(Node->getOperand(i).getValueType() != MVT::Other &&
Node->getOperand(i).getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
+
+ // Get/emit the operand.
+ unsigned VReg = getVR(Node->getOperand(i));
+ MI->addRegOperand(VReg, MachineOperand::Use);
- MI->addRegOperand(getVR(Node->getOperand(i)), MachineOperand::Use);
+ // Verify that it is right.
+ assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+ assert(II.OpInfo[i+NumResults].RegClass &&
+ "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
+ "Register class of operand and regclass of use don't agree!");
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
MI->addZeroExtImm64Operand(C->getValue());
@@ -979,7 +988,15 @@
assert(Node->getOperand(i).getValueType() != MVT::Other &&
Node->getOperand(i).getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
- MI->addRegOperand(getVR(Node->getOperand(i)), MachineOperand::Use);
+ unsigned VReg = getVR(Node->getOperand(i));
+ MI->addRegOperand(VReg, MachineOperand::Use);
+
+ // Verify that it is right.
+ assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+ assert(II.OpInfo[i+NumResults].RegClass &&
+ "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
+ "Register class of operand and regclass of use don't agree!");
}
}