Implement sseregparm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46764 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td
index 4d674f7..eb88ce3 100644
--- a/lib/Target/X86/X86CallingConv.td
+++ b/lib/Target/X86/X86CallingConv.td
@@ -61,6 +61,15 @@
CCDelegateTo<RetCC_X86Common>
]>;
+// X86-32 SSEregparm return-value convention.
+def RetCC_X86_32_SSE : CallingConv<[
+ // The X86-32 sseregparm calling convention returns FP values in XMM0 if the
+ // target has SSE2, otherwise it is the C calling convention.
+ CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
+ CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
+ CCDelegateTo<RetCC_X86Common>
+]>;
+
// X86-64 C return-value convention.
def RetCC_X86_64_C : CallingConv<[
// The X86-64 calling convention always returns FP values in XMM0.
@@ -69,12 +78,12 @@
CCDelegateTo<RetCC_X86Common>
]>;
-
-
// This is the root return-value convention for the X86-32 backend.
def RetCC_X86_32 : CallingConv<[
// If FastCC, use RetCC_X86_32_Fast.
CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
+ // If SSECC, use RetCC_X86_32_SSE.
+ CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
// Otherwise, use RetCC_X86_32_C.
CCDelegateTo<RetCC_X86_32_C>
]>;
@@ -179,6 +188,11 @@
// Handles byval parameters.
CCIfByVal<CCPassByVal<4, 4>>,
+ // The first 3 float or double arguments, if marked 'inreg' and if the call
+ // is not a vararg call and if SSE2 is available, are passed in SSE registers.
+ CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], CCIfSubtarget<"hasSSE2()",
+ CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
+
// Integer/Float values get stored in stack slots that are 4 bytes in
// size and 4-byte aligned.
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index af993e1..091ce18 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1137,9 +1137,9 @@
RC = X86::GR32RegisterClass;
else if (Is64Bit && RegVT == MVT::i64)
RC = X86::GR64RegisterClass;
- else if (Is64Bit && RegVT == MVT::f32)
+ else if (RegVT == MVT::f32)
RC = X86::FR32RegisterClass;
- else if (Is64Bit && RegVT == MVT::f64)
+ else if (RegVT == MVT::f64)
RC = X86::FR64RegisterClass;
else {
assert(MVT::isVector(RegVT));