commit 51552f65806f94dfb437e143ad50b253ef276026
author Dale Johannesen <dalej@apple.com> Tue Feb 05 20:46:33 2008 +0000
committer Dale Johannesen <dalej@apple.com> Tue Feb 05 20:46:33 2008 +0000
tree 99e2805654e38c96260cea04760cd4dc32479311
parent 86f26d2861aa414c18244b164aeefa2bb5ec5a58

Implement sseregparm.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46764 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index af993e1..091ce18 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1137,9 +1137,9 @@
         RC = X86::GR32RegisterClass;
       else if (Is64Bit && RegVT == MVT::i64)
         RC = X86::GR64RegisterClass;
-      else if (Is64Bit && RegVT == MVT::f32)
+      else if (RegVT == MVT::f32)
         RC = X86::FR32RegisterClass;
-      else if (Is64Bit && RegVT == MVT::f64)
+      else if (RegVT == MVT::f64)
         RC = X86::FR64RegisterClass;
       else {
         assert(MVT::isVector(RegVT));