commit 51b16f473759c1546acbf308a5d3f3e7bf3ea23c
author Bill Wendling <isanbard@gmail.com> Sat May 30 01:09:53 2009 +0000
committer Bill Wendling <isanbard@gmail.com> Sat May 30 01:09:53 2009 +0000
tree 1c33a0bd47e7b0fc26b2c57cb67cbb6b62e23ef4
parent 4d4eab219a96203f58452b39b4e94e234dfe4007

Untabification.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 0136f90..882ee3a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -6974,7 +6974,7 @@
 
   // Insert instructions into newMBB based on incoming instruction
   assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
-	 "unexpected number of operands");
+         "unexpected number of operands");
   DebugLoc dl = bInstr->getDebugLoc();
   MachineOperand& destOper = bInstr->getOperand(0);
   MachineOperand* argOpers[2 + X86AddrNumOperands];
@@ -7084,7 +7084,7 @@
   // Insert instructions into newMBB based on incoming instruction
   // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
   assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
-	 "unexpected number of operands");
+         "unexpected number of operands");
   MachineOperand& dest1Oper = bInstr->getOperand(0);
   MachineOperand& dest2Oper = bInstr->getOperand(1);
   MachineOperand* argOpers[2 + X86AddrNumOperands];
@@ -7131,7 +7131,7 @@
 
   int valArgIndx = lastAddrIndx + 1;
   assert((argOpers[valArgIndx]->isReg() ||
-	  argOpers[valArgIndx]->isImm()) &&
+          argOpers[valArgIndx]->isImm()) &&
          "invalid operand");
   unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
   unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
@@ -7143,9 +7143,9 @@
     MIB.addReg(tt1);
   (*MIB).addOperand(*argOpers[valArgIndx]);
   assert(argOpers[valArgIndx + 1]->isReg() ==
-	 argOpers[valArgIndx]->isReg());
+         argOpers[valArgIndx]->isReg());
   assert(argOpers[valArgIndx + 1]->isImm() ==
-	 argOpers[valArgIndx]->isImm());
+         argOpers[valArgIndx]->isImm());
   if (argOpers[valArgIndx + 1]->isReg())
     MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
   else
@@ -7226,7 +7226,7 @@
   DebugLoc dl = mInstr->getDebugLoc();
   // Insert instructions into newMBB based on incoming instruction
   assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
-	 "unexpected number of operands");
+         "unexpected number of operands");
   MachineOperand& destOper = mInstr->getOperand(0);
   MachineOperand* argOpers[2 + X86AddrNumOperands];
   int numArgs = mInstr->getNumOperands() - 1;