Add 8-bit insts. zext behaviour is not modelled yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70722 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp
index c84c96e..579da6e 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -32,16 +32,24 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
- if (DestRC != SrcRC) {
- // Not yet supported!
- return false;
- }
-
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
- BuildMI(MBB, I, DL, get(MSP430::MOV16rr), DestReg).addReg(SrcReg);
- return true;
+ if (DestRC == SrcRC) {
+ unsigned Opc;
+ if (DestRC == &MSP430::GR16RegClass) {
+ Opc = MSP430::MOV16rr;
+ } else if (DestRC == &MSP430::GR8RegClass) {
+ Opc = MSP430::MOV8rr;
+ } else {
+ return false;
+ }
+
+ BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
+ return true;
+ }
+
+ return false;
}
bool
@@ -53,8 +61,9 @@
switch (MI.getOpcode()) {
default:
return false;
+ case MSP430::MOV8rr:
case MSP430::MOV16rr:
- assert(MI.getNumOperands() >= 2 &&
+ assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid register-register move instruction");