Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index c10900c..17b50bd 100644
--- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -99,12 +99,24 @@
AggressiveAntiDepBreaker::
-AggressiveAntiDepBreaker(MachineFunction& MFi) :
+AggressiveAntiDepBreaker(MachineFunction& MFi,
+ TargetSubtarget::ExcludedRCVector& ExcludedRCs) :
AntiDepBreaker(), MF(MFi),
MRI(MF.getRegInfo()),
TRI(MF.getTarget().getRegisterInfo()),
AllocatableSet(TRI->getAllocatableSet(MF)),
State(NULL), SavedState(NULL) {
+ /* Remove all registers from excluded RCs from the allocatable
+ register set. */
+ for (unsigned i = 0, e = ExcludedRCs.size(); i < e; ++i) {
+ BitVector NotRenameable = TRI->getAllocatableSet(MF, ExcludedRCs[i]).flip();
+ AllocatableSet &= NotRenameable;
+ }
+
+ DEBUG(errs() << "AntiDep Renameable Registers:");
+ DEBUG(for (int r = AllocatableSet.find_first(); r != -1;
+ r = AllocatableSet.find_next(r))
+ errs() << " " << TRI->getName(r));
}
AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.h b/lib/CodeGen/AggressiveAntiDepBreaker.h
index c512168..fb5b869 100644
--- a/lib/CodeGen/AggressiveAntiDepBreaker.h
+++ b/lib/CodeGen/AggressiveAntiDepBreaker.h
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/Target/TargetSubtarget.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
@@ -112,7 +113,7 @@
/// AllocatableSet - The set of allocatable registers.
/// We'll be ignoring anti-dependencies on non-allocatable registers,
/// because they may not be safe to break.
- const BitVector AllocatableSet;
+ BitVector AllocatableSet;
/// State - The state used to identify and rename anti-dependence
/// registers.
@@ -124,7 +125,8 @@
AggressiveAntiDepState *SavedState;
public:
- AggressiveAntiDepBreaker(MachineFunction& MFi);
+ AggressiveAntiDepBreaker(MachineFunction& MFi,
+ TargetSubtarget::ExcludedRCVector& ExcludedRCs);
~AggressiveAntiDepBreaker();
/// GetMaxTrials - As anti-dependencies are broken, additional
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 3ed61a2..5917e76 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -216,13 +216,14 @@
// Check for explicit enable/disable of post-ra scheduling.
TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
+ TargetSubtarget::ExcludedRCVector ExcludedRCs;
if (EnablePostRAScheduler.getPosition() > 0) {
if (!EnablePostRAScheduler)
return false;
} else {
// Check that post-RA scheduling is enabled for this target.
const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
- if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode))
+ if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, ExcludedRCs))
return false;
}
@@ -243,7 +244,7 @@
(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
AntiDepBreaker *ADB =
((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
- (AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn) :
+ (AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn, ExcludedRCs) :
((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
(AntiDepBreaker *)new CriticalAntiDepBreaker(Fn) : NULL));
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index e721a7f..c94f9fe 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -17,6 +17,7 @@
#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtarget.h"
+#include "ARMBaseRegisterInfo.h"
#include <string>
namespace llvm {
@@ -129,8 +130,11 @@
/// enablePostRAScheduler - True at 'More' optimization except
/// for Thumb1.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
- TargetSubtarget::AntiDepBreakMode& mode) const {
- mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ TargetSubtarget::AntiDepBreakMode& Mode,
+ ExcludedRCVector& ExcludedRCs) const {
+ Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ ExcludedRCs.clear();
+ ExcludedRCs.push_back(&ARM::GPRRegClass);
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index 1c8cefa..f18def1 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -219,8 +219,10 @@
/// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
/// at 'More' optimization level.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
- TargetSubtarget::AntiDepBreakMode& mode) const {
- mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ TargetSubtarget::AntiDepBreakMode& Mode,
+ ExcludedRCVector& ExcludedRCs) const {
+ Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ ExcludedRCs.clear();
return OptLevel >= CodeGenOpt::Default;
}
};