Add named timer groups for the different stages of register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121604 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocBase.h b/lib/CodeGen/RegAllocBase.h
index 7d13327..438a7d1 100644
--- a/lib/CodeGen/RegAllocBase.h
+++ b/lib/CodeGen/RegAllocBase.h
@@ -153,6 +153,9 @@
void verify();
#endif
+ // Use this group name for NamedRegionTimer.
+ static const char *TimerGroupName;
+
private:
void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index 3c84543..eb1b907 100644
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -42,6 +42,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Timer.h"
#include <cstdlib>
@@ -56,6 +57,8 @@
VerifyRegAlloc("verify-regalloc",
cl::desc("Verify live intervals before renaming"));
+const char *RegAllocBase::TimerGroupName = "Register Allocation";
+
namespace {
class PhysicalRegisterDescription : public AbstractRegisterDescription {
@@ -204,6 +207,7 @@
}
void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
+ NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
TRI = &vrm.getTargetRegInfo();
MRI = &vrm.getRegInfo();
VRM = &vrm;
@@ -364,6 +368,7 @@
// Add newly allocated physical registers to the MBB live in sets.
void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
+ NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
MBBVec liveInMBBs;
MachineBasicBlock &entryMBB = *MF->begin();
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 01946c0..aab2848 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -35,6 +35,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Timer.h"
using namespace llvm;
@@ -58,7 +59,7 @@
/// Return the pass name.
virtual const char* getPassName() const {
- return "Basic Register Allocator";
+ return "Greedy Register Allocator";
}
/// RAGreedy analysis usage.
@@ -254,17 +255,19 @@
// Try to reassign interfering physical register. Priority among
// PhysRegSpillCands does not matter yet, because the reassigned virtual
// registers will still be assigned to physical registers.
- for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
- PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
- if (reassignInterferences(VirtReg, *PhysRegI))
- // Reassignment successfull. The caller may allocate now to this PhysReg.
- return *PhysRegI;
+ {
+ NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
+ for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
+ PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI)
+ if (reassignInterferences(VirtReg, *PhysRegI))
+ // Reassignment successfull. Allocate now to this PhysReg.
+ return *PhysRegI;
}
-
PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
ReassignCands.end());
// Try to spill another interfering reg with less spill weight.
+ NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
//
// FIXME: do this in two steps: (1) check for unspillable interferences while
// accumulating spill weight; (2) spill the interferences with lowest
@@ -305,8 +308,11 @@
addMBBLiveIns(MF);
// Run rewriter
- std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
- rewriter->runOnMachineFunction(*MF, *VRM, LIS);
+ {
+ NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
+ std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
+ rewriter->runOnMachineFunction(*MF, *VRM, LIS);
+ }
// The pass output is in VirtRegMap. Release all the transient data.
releaseMemory();