update a couple of references to SSARegMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45468 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index ce07074..f506b3e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -606,7 +606,7 @@
SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
}
- // TODO: Add tracking info to SSARegMap of which vregs are subregs
+ // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
// to allow coalescing in the allocator
// If the node is only used by a CopyToReg and the dest reg is a vreg, use
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index da8b39f..d48e1f9 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1410,8 +1410,8 @@
(*I)->eraseFromParent();
}
- // Transfer sub-registers info to SSARegMap now that coalescing information
- // is complete.
+ // Transfer sub-registers info to MachineRegisterInfo now that coalescing
+ // information is complete.
RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1);
while (!SubRegIdxes.empty()) {
std::pair<unsigned, unsigned> RI = SubRegIdxes.back();