ARM: update peephole optimization.
More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".
rdar: 11725965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e30f6d2..58f4e16 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1875,7 +1875,9 @@
}
// Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1).
- if (SrcReg2 != 0 && Instr.getOpcode() == ARM::SUBrr &&
+ if (SrcReg2 != 0 &&
+ (Instr.getOpcode() == ARM::SUBrr ||
+ Instr.getOpcode() == ARM::t2SUBrr) &&
((Instr.getOperand(1).getReg() == SrcReg &&
Instr.getOperand(2).getReg() == SrcReg2) ||
(Instr.getOperand(1).getReg() == SrcReg2 &&
@@ -1976,6 +1978,12 @@
case ARMCC::LT:
case ARMCC::GT:
case ARMCC::LE:
+ case ARMCC::HS:
+ case ARMCC::LS:
+ case ARMCC::HI:
+ case ARMCC::LO:
+ case ARMCC::EQ:
+ case ARMCC::NE:
// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
// on CMP needs to be updated to be based on SUB.
// Push the condition code operands to OperandsToUpdate.
@@ -2023,7 +2031,15 @@
case ARMCC::GE: NewCC = ARMCC::LE; break;
case ARMCC::LT: NewCC = ARMCC::GT; break;
case ARMCC::GT: NewCC = ARMCC::LT; break;
- case ARMCC::LE: NewCC = ARMCC::GT; break;
+ case ARMCC::LE: NewCC = ARMCC::GE; break;
+ case ARMCC::HS: NewCC = ARMCC::LS; break;
+ case ARMCC::LS: NewCC = ARMCC::HS; break;
+ case ARMCC::HI: NewCC = ARMCC::LO; break;
+ case ARMCC::LO: NewCC = ARMCC::HI; break;
+ case ARMCC::EQ:
+ case ARMCC::NE:
+ NewCC = CC;
+ break;
}
OperandsToUpdate[i]->setImm(NewCC);
}