Added a check in the preRA scheduler for potential interference on a
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.
Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 202f7ab..24a1937 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -81,6 +81,7 @@
SUnit *SU = NewSUnit(Old->getNode());
SU->OrigNode = Old->OrigNode;
SU->Latency = Old->Latency;
+ SU->isVRegCycle = Old->isVRegCycle;
SU->isCall = Old->isCall;
SU->isTwoAddress = Old->isTwoAddress;
SU->isCommutable = Old->isCommutable;
@@ -341,6 +342,10 @@
assert(N->getNodeId() == -1 && "Node already inserted!");
N->setNodeId(NodeSUnit->NodeNum);
+ // Set isVRegCycle if the node operands are live into and value is live out
+ // of a single block loop.
+ InitVRegCycleFlag(NodeSUnit);
+
// Compute NumRegDefsLeft. This must be done before AddSchedEdges.
InitNumRegDefsLeft(NodeSUnit);
@@ -507,6 +512,47 @@
}
}
+// Set isVRegCycle if this node's single use is CopyToReg and its only active
+// data operands are CopyFromReg.
+//
+// This is only relevant for single-block loops, in which case the VRegCycle
+// node is likely an induction variable in which the operand and target virtual
+// registers should be coalesced (e.g. pre/post increment values). Setting the
+// isVRegCycle flag helps the scheduler prioritize other uses of the same
+// CopyFromReg so that this node becomes the virtual register "kill". This
+// avoids interference between the values live in and out of the block and
+// eliminates a copy inside the loop.
+void ScheduleDAGSDNodes::InitVRegCycleFlag(SUnit *SU) {
+ if (!BB->isSuccessor(BB))
+ return;
+
+ SDNode *N = SU->getNode();
+ if (N->getGluedNode())
+ return;
+
+ if (!N->hasOneUse() || N->use_begin()->getOpcode() != ISD::CopyToReg)
+ return;
+
+ bool FoundLiveIn = false;
+ for (SDNode::op_iterator OI = N->op_begin(), E = N->op_end(); OI != E; ++OI) {
+ EVT OpVT = OI->getValueType();
+ assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
+
+ if (OpVT == MVT::Other)
+ continue; // ignore chain operands
+
+ if (isPassiveNode(OI->getNode()))
+ continue; // ignore constants and such
+
+ if (OI->getNode()->getOpcode() != ISD::CopyFromReg)
+ return;
+
+ FoundLiveIn = true;
+ }
+ if (FoundLiveIn)
+ SU->isVRegCycle = true;
+}
+
void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
assert(SU->NumRegDefsLeft == 0 && "expect a new node");
for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {