Tidy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106383 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp
index 16d3247..0e1edc4 100644
--- a/lib/CodeGen/IfConversion.cpp
+++ b/lib/CodeGen/IfConversion.cpp
@@ -994,7 +994,7 @@
if (TII->ReverseBranchCondition(Cond))
assert(false && "Unable to reverse branch condition!");
- // Initialize liveins to the first BB. These are potentiall re-defined by
+ // Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
SmallSet<unsigned, 4> Redefs;
InitPredRedefs(CvtBBI->BB, Redefs, TRI);
@@ -1085,7 +1085,7 @@
}
}
- // Initialize liveins to the first BB. These are potentiall re-defined by
+ // Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
SmallSet<unsigned, 4> Redefs;
InitPredRedefs(CvtBBI->BB, Redefs, TRI);
@@ -1205,7 +1205,7 @@
// Remove the conditional branch from entry to the blocks.
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
- // Initialize liveins to the first BB. These are potentiall re-defined by
+ // Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
SmallSet<unsigned, 4> Redefs;
InitPredRedefs(BBI1->BB, Redefs, TRI);
@@ -1307,7 +1307,7 @@
llvm_unreachable(0);
}
- // If the predicated instruction now re-defines a register as the result of
+ // If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
UpdatePredRedefs(I, Redefs, TRI, true);
}
@@ -1348,7 +1348,7 @@
}
}
- // If the predicated instruction now re-defines a register as the result of
+ // If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
UpdatePredRedefs(MI, Redefs, TRI, true);
}