diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index ea20a3e..1857f89 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -8,7 +8,7 @@
 #include "SchedPriorities.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
 #include "llvm/Target/TargetMachine.h"
@@ -631,14 +631,14 @@
 static void
 RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
 {
-  MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
+  MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
   const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
   
 #ifndef NDEBUG
   // Lets make sure we didn't lose any instructions, except possibly
   // some NOPs from delay slots.  Also, PHIs are not included in the schedule.
   unsigned numInstr = 0;
-  for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
+  for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
     if (! mii.isNop((*I)->getOpCode()) &&
 	! mii.isDummyPhiInstr((*I)->getOpCode()))
       ++numInstr;
@@ -650,7 +650,7 @@
     return;				// empty basic block!
   
   // First find the dummy instructions at the start of the basic block
-  MachineCodeForBasicBlock::iterator I = mvec.begin();
+  MachineBasicBlock::iterator I = mvec.begin();
   for ( ; I != mvec.end(); ++I)
     if (! mii.isDummyPhiInstr((*I)->getOpCode()))
       break;
@@ -1220,7 +1220,7 @@
   // fill delay slots, otherwise, just discard them.
   //  
   unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
-  MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(node->getBB());
+  MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB());
   assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
          "Incorrect instr. index in basic block for brInstr");
   
@@ -1325,8 +1325,8 @@
   // Simply passing in an empty delayNodeVec will have this effect.
   // 
   delayNodeVec.clear();
-  const MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb);
-  for (unsigned i=0; i < bbMvec.size(); i++)
+  const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
+  for (unsigned i=0; i < bbMvec.size(); ++i)
     if (bbMvec[i] != brInstr &&
         mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
       {
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index c3262c0..cc3e5b5 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -9,7 +9,7 @@
 #include "SchedGraph.h"
 #include "llvm/CodeGen/InstrSelection.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Target/MachineRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Function.h"
@@ -387,7 +387,7 @@
   // all preceding instructions in the basic block.  Use 0 latency again.
   // 
   const BasicBlock* bb = firstBrNode->getBB();
-  const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
+  const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
   for (unsigned i=0, N=mvec.size(); i < N; i++) 
     {
       if (mvec[i] == termMvec[first])   // reached the first branch
@@ -480,7 +480,7 @@
 // 
 void
 SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
-                           MachineCodeForBasicBlock& bbMvec,
+                           MachineBasicBlock& bbMvec,
                            const TargetMachine& target)
 {
   const MachineInstrInfo& mii = target.getInstrInfo();
@@ -753,7 +753,7 @@
   
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.
-  const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
+  const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
   for (unsigned i=0; i < mvec.size(); i++)
     if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
       {
@@ -789,7 +789,7 @@
         
         // Find the machine instruction that makes a copy of inval to (*PI).
         // This must be in the current basic block (bb).
-        const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI);
+        const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI);
         const MachineInstr* theCopy = NULL;
         for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
           if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
@@ -882,7 +882,7 @@
   // 
   //----------------------------------------------------------------
       
-  MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb);
+  MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
   
   // First, add edges to the terminator instruction of the basic block.
   this->addCDEdges(bb->getTerminator(), target);
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
index 83ce0a7..83f7927 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
@@ -11,7 +11,7 @@
 #include "llvm/CodeGen/InstrSelectionSupport.h"
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Target/MachineRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -145,7 +145,7 @@
   for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI)
     for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) {
       MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II);
-      MachineCodeForBasicBlock &MCBB = MachineCodeForBasicBlock::get(BI);
+      MachineBasicBlock &MCBB = MachineBasicBlock::get(BI);
       MCBB.insert(MCBB.end(), mvec.begin(), mvec.end());
     }
 
@@ -205,7 +205,7 @@
       Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec);
       
       // get an iterator to machine instructions in the BB
-      MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(BB);
+      MachineBasicBlock& bbMvec = MachineBasicBlock::get(BB);
       
       bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
     }  // for each Phi Instr in BB
@@ -227,11 +227,11 @@
   
   assert (FirstMIOfTerm && "No Machine Instrs for terminator");
   
-  MachineCodeForBasicBlock &bbMvec = MachineCodeForBasicBlock::get(BB);
+  MachineBasicBlock &bbMvec = MachineBasicBlock::get(BB);
 
   // find the position of first machine instruction generated by the
   // terminator of this BB
-  MachineCodeForBasicBlock::iterator MCIt =
+  MachineBasicBlock::iterator MCIt =
     std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm);
 
   assert( MCIt != bbMvec.end() && "Start inst of terminator not found");
diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
index 0b2979b..54de63e 100644
--- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
+++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
@@ -7,10 +7,9 @@
 #include "BBLiveVar.h"
 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/CFG.h"
 #include "Support/SetOperations.h"
-#include <iostream>
 
 /// BROKEN: Should not include sparc stuff directly into here
 #include "../../Target/Sparc/SparcInternals.h"  //  Only for PHI defn
@@ -51,10 +50,10 @@
 
 void BBLiveVar::calcDefUseSets() {
   // get the iterator for machine instructions
-  const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(&BB);
+  const MachineBasicBlock &MIVec = MachineBasicBlock::get(&BB);
 
   // iterate over all the machine instructions in BB
-  for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
+  for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
          MIE = MIVec.rend(); MII != MIE; ++MII) {
     const MachineInstr *MI = *MII;
     
diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
index e63d96c..198afed 100644
--- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
+++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
@@ -8,12 +8,11 @@
 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
 #include "BBLiveVar.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/CFG.h"
 #include "Support/PostOrderIterator.h"
 #include "Support/SetOperations.h"
 #include "Support/CommandLine.h"
-#include <iostream>
 
 static RegisterAnalysis<FunctionLiveVarInfo>
 X("livevar", "Live Variable Analysis");
@@ -241,7 +240,7 @@
 //-----------------------------------------------------------------------------
 
 void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
-  const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BB);
+  const MachineBasicBlock &MIVec = MachineBasicBlock::get(BB);
 
   if (DEBUG_LV >= LV_DEBUG_Instr)
     std::cerr << "\n======For BB " << BB->getName()
@@ -252,7 +251,7 @@
   set_union(CurSet, *SetAI);                   // CurSet now contains OutSet
 
   // iterate over all the machine instructions in BB
-  for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
+  for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
          MIE = MIVec.rend(); MII != MIE; ++MII) {  
     // MI is cur machine inst
     const MachineInstr *MI = *MII;  
diff --git a/lib/Target/SparcV9/MappingInfo.cpp b/lib/Target/SparcV9/MappingInfo.cpp
index e207c20..087fba2 100644
--- a/lib/Target/SparcV9/MappingInfo.cpp
+++ b/lib/Target/SparcV9/MappingInfo.cpp
@@ -10,7 +10,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Module.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include <map>
 using std::vector;
@@ -126,7 +126,7 @@
   unsigned i = 0;
   for (Function::iterator BI = FI.begin(), BE = FI.end(); 
        BI != BE; ++BI){
-    MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI);
+    MachineBasicBlock &miBB = MachineBasicBlock::get(BI);
     BBkey[miBB[0]] = i;
     i = i+(miBB.size());
   }
@@ -136,9 +136,9 @@
 void getMappingInfoForFunction::create_MI_to_number_Key(Function &FI){
   for (Function::iterator BI=FI.begin(), BE=FI.end(); 
        BI != BE; ++BI){
-    MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI);
+    MachineBasicBlock &miBB = MachineBasicBlock::get(BI);
     unsigned j = 0;
-    for(MachineCodeForBasicBlock::iterator miI=miBB.begin(), miE=miBB.end();
+    for(MachineBasicBlock::iterator miI=miBB.begin(), miE=miBB.end();
 	miI!=miE; ++miI, ++j){
       MIkey[*miI]=j;
     }
@@ -151,7 +151,7 @@
   unsigned bb=0;
   for (Function::iterator BI = FI.begin(), 
 	 BE = FI.end(); BI != BE; ++BI, ++bb){
-    MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI);
+    MachineBasicBlock &miBB = MachineBasicBlock::get(BI);
     writeNumber(bb);
     //Out << " BB: "<<(void *)BI<<"\n";
     //for(int i=0; i<miBB.size(); ++i)
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index f414347..3c4dfb2 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -13,7 +13,7 @@
 
 #include "SparcInternals.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
@@ -469,11 +469,11 @@
   toAsm << getID(BB) << ":\n";
 
   // Get the vector of machine instructions corresponding to this bb.
-  const MachineCodeForBasicBlock &MIs = MachineCodeForBasicBlock::get(BB);
-  MachineCodeForBasicBlock::const_iterator MII = MIs.begin(), MIE = MIs.end();
+  const MachineBasicBlock &MIs = MachineBasicBlock::get(BB);
 
   // Loop over all of the instructions in the basic block...
-  for (; MII != MIE; ++MII)
+  for (MachineBasicBlock::const_iterator MII = MIs.begin(), MIE = MIs.end();
+       MII != MIE; ++MII)
     emitMachineInst(*MII);
   toAsm << "\n";  // Seperate BB's with newlines
 }
diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index fb83cbb..b41290e 100644
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -1,16 +1,12 @@
-// $Id$ -*-c++-*-
-//***************************************************************************
-// File:
-//	PeepholeOpts.h
+//===-- PeepholeOpts.cpp --------------------------------------------------===//
 // 
-// Purpose:
-//	Support for performing several peephole opts in one or a few passes
-//      over the machine code of a method.
-//**************************************************************************/
-
+// Support for performing several peephole opts in one or a few passes over the
+// machine code of a method.
+//
+//===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/PeepholeOpts.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MachineInstrInfo.h"
@@ -18,15 +14,11 @@
 #include "llvm/BasicBlock.h"
 #include "llvm/Pass.h"
 
-
-//********************* Internal Class Declarations ************************/
-
-
 //************************* Internal Functions *****************************/
 
 inline void
-DeleteInstruction(MachineCodeForBasicBlock& mvec,
-                  MachineCodeForBasicBlock::iterator& BBI,
+DeleteInstruction(MachineBasicBlock& mvec,
+                  MachineBasicBlock::iterator& BBI,
                   const TargetMachine& target)
 {
   // Check if this instruction is in a delay slot of its predecessor.
@@ -55,8 +47,8 @@
 
 
 inline bool
-RemoveUselessCopies(MachineCodeForBasicBlock& mvec,
-                    MachineCodeForBasicBlock::iterator& BBI,
+RemoveUselessCopies(MachineBasicBlock& mvec,
+                    MachineBasicBlock::iterator& BBI,
                     const TargetMachine& target)
 {
   if (target.getOptInfo().IsUselessCopy(*BBI))
@@ -72,8 +64,8 @@
 
 class PeepholeOpts: public BasicBlockPass {
   const TargetMachine &target;
-  bool visit(MachineCodeForBasicBlock& mvec,
-             MachineCodeForBasicBlock::iterator BBI) const;
+  bool visit(MachineBasicBlock& mvec,
+             MachineBasicBlock::iterator BBI) const;
 public:
   PeepholeOpts(const TargetMachine &T): target(T) { }
   bool runOnBasicBlock(BasicBlock &BB); // apply this pass to each BB
@@ -90,8 +82,8 @@
  * instruction before MI, but not 
  */
 bool
-PeepholeOpts::visit(MachineCodeForBasicBlock& mvec,
-                    MachineCodeForBasicBlock::iterator BBI) const
+PeepholeOpts::visit(MachineBasicBlock& mvec,
+                    MachineBasicBlock::iterator BBI) const
 {
   bool changed = false;
 
@@ -108,16 +100,16 @@
 PeepholeOpts::runOnBasicBlock(BasicBlock &BB)
 {
   // Get the machine instructions for this BB
-  MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(&BB);
+  MachineBasicBlock& mvec = MachineBasicBlock::get(&BB);
 
   // Iterate over all machine instructions in the BB
   // Use a reverse iterator to allow deletion of MI or any instruction after it.
   // Insertions or deletions *before* MI are not safe.
   // 
-  for (MachineCodeForBasicBlock::reverse_iterator RI=mvec.rbegin(),
+  for (MachineBasicBlock::reverse_iterator RI=mvec.rbegin(),
          RE=mvec.rend(); RI != RE; )
     {
-      MachineCodeForBasicBlock::iterator BBI = RI.base()-1; // save before incr
+      MachineBasicBlock::iterator BBI = RI.base()-1; // save before incr
       ++RI;             // pre-increment to delete MI or after it
       visit(mvec, BBI);
     }
diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index adb1490..bc6514f 100644
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -12,7 +12,7 @@
 #include "SparcInternals.h"
 #include "SparcRegClassInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/InstrSelectionSupport.h"
@@ -118,7 +118,7 @@
       mvec.push_back(M);
     }
 
-  MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(&F.getEntryNode());
+  MachineBasicBlock& bbMvec = MachineBasicBlock::get(&F.getEntryNode());
   bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
 }
 
@@ -134,7 +134,7 @@
                                         (int64_t)0);
         Restore->SetMachineOperandReg(2, Target.getRegInfo().getZeroRegNum());
         
-        MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(I);
+        MachineBasicBlock& bbMvec = MachineBasicBlock::get(I);
         MachineCodeForInstruction &termMvec =
           MachineCodeForInstruction::get(TermInst);