Add selection DAG nodes for subreg insert/extract. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 25f0320..4131ed9 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -957,7 +957,23 @@
AddLegalizedOperand(SDOperand(Node, i), Tmp1);
}
return Tmp2;
-
+ case ISD::EXTRACT_SUBREG: {
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
+ assert(idx && "Operand must be a constant");
+ Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+ }
+ break;
+ case ISD::INSERT_SUBREG: {
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
+ ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
+ assert(idx && "Operand must be a constant");
+ Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+ }
+ break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 9b146ee..d4d984b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3455,7 +3455,10 @@
case ISD::SHL_PARTS: return "shl_parts";
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
-
+
+ case ISD::EXTRACT_SUBREG: return "extract_subreg";
+ case ISD::INSERT_SUBREG: return "insert_subreg";
+
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";