commit 55ad1f22b4554be3a9547fe7a8d84ce05b3d5c72
author Anton Korobeynikov <asl@math.spbu.ru> Sat Jun 27 12:59:03 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Sat Jun 27 12:59:03 2009 +0000
tree c9d475802136c0c143cc47c7a0cac93741e60129
parent a98cbc554ca2cd40426e7c3ff8d1467da32e195d

Simplify a bit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74385 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 034b697..5d77e99 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -138,9 +138,11 @@
                                  const MachineInstr *Orig) const {
   DebugLoc dl = Orig->getDebugLoc();
   if (Orig->getOpcode() == ARM::MOVi2pieces) {
-    RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
-                         Orig->getOperand(2).getImm(),
-                         Orig->getOperand(3).getReg(), this, dl);
+    RI.emitLoadConstPool(MBB, I, this, dl,
+                         DestReg,
+                         Orig->getOperand(1).getImm(),
+                         (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
+                         Orig->getOperand(3).getReg());
     return;
   }