Fix SPU BE to use all the available return registers.
llc used to assert on the added testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/call.ll b/test/CodeGen/CellSPU/call.ll
index eb7cf2c..559b266 100644
--- a/test/CodeGen/CellSPU/call.ll
+++ b/test/CodeGen/CellSPU/call.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s
; RUN: grep brsl %t1.s | count 1
-; RUN: grep brasl %t1.s | count 1
-; RUN: grep stqd %t1.s | count 80
+; RUN: grep brasl %t1.s | count 2
+; RUN: grep stqd %t1.s | count 82
; RUN: llc < %s -march=cellspu | FileCheck %s
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
@@ -29,3 +29,25 @@
entry:
ret i32 0
}
+
+; check that struct is passed in r3->
+; assert this by changing the second field in the struct
+%0 = type { i32, i32, i32 }
+declare %0 @callee()
+define %0 @test_structret()
+{
+;CHECK: stqd $lr, 16($sp)
+;CHECK: stqd $sp, -48($sp)
+;CHECK: ai $sp, $sp, -48
+;CHECK: brasl $lr, callee
+ %rv = call %0 @callee()
+;CHECK: ai $4, $4, 1
+;CHECK: lqd $lr, 64($sp)
+;CHECK: ai $sp, $sp, 48
+;CHECK: bi $lr
+ %oldval = extractvalue %0 %rv, 1
+ %newval = add i32 %oldval,1
+ %newrv = insertvalue %0 %rv, i32 %newval, 1
+ ret %0 %newrv
+}
+