commit 55e0249a9e49c060a94ace9c6bd36546ff24620f
author Anton Korobeynikov <asl@math.spbu.ru> Sun May 03 13:13:51 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Sun May 03 13:13:51 2009 +0000
tree cec4b96dc3eb067129aeadaa1634f74537e4ff97
parent d7d974a5093b80ba90f9c9154c6b537397e227de

Add libcall expansion for 16 and 128 bit muls

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70749 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 697caa6..9890876 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3315,10 +3315,14 @@
         }
         break;
       case ISD::MUL:
+        if (VT == MVT::i16)
+          LC = RTLIB::MUL_I16;
         if (VT == MVT::i32)
           LC = RTLIB::MUL_I32;
         else if (VT == MVT::i64)
           LC = RTLIB::MUL_I64;
+        else if (VT == MVT::i128)
+          LC = RTLIB::MUL_I128;
         break;
       case ISD::FPOW:
         LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,