Implement 64-bit undef, sub, shl/shr, srem/urem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index 657ff6c..36f6805 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -52,7 +52,8 @@
// minor pessimization that saves us from having to worry about
// keeping the offsets up to date later when we emit long branch glue.
return 8;
- case PPC::IMPLICIT_DEF_GPR: // no asm emitted
+ case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
+ case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
case PPC::IMPLICIT_DEF_F4: // no asm emitted
case PPC::IMPLICIT_DEF_F8: // no asm emitted
return 0;
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index a530b1e..f1c0e07 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -125,7 +125,8 @@
default:
MCE.emitWordBE(getBinaryCodeForInstr(*I));
break;
- case PPC::IMPLICIT_DEF_GPR:
+ case PPC::IMPLICIT_DEF_GPRC:
+ case PPC::IMPLICIT_DEF_G8RC:
case PPC::IMPLICIT_DEF_F8:
case PPC::IMPLICIT_DEF_F4:
case PPC::IMPLICIT_DEF_VRRC:
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index a417a2d..5122b56 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -58,6 +58,8 @@
// PowerPC has no SREM/UREM instructions
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
// We don't support sin/cos/sqrt/fmod
setOperationAction(ISD::FSIN , MVT::f64, Expand);
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 0f6c693..99294c5 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -54,6 +54,14 @@
//===----------------------------------------------------------------------===//
+// Pseudo instructions.
+//
+
+def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; $rD = IMPLICIT_DEF_G8RC",
+ [(set G8RC:$rD, (undef))]>;
+
+
+//===----------------------------------------------------------------------===//
// Fixed point instructions.
//
@@ -134,7 +142,12 @@
"addis $rD, $rA, $imm", IntGeneral,
[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
-
+def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
+ "subfic $rD, $rA, $imm", IntGeneral,
+ [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
+def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ "subf $rT, $rA, $rB", IntGeneral,
+ [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
@@ -326,9 +339,9 @@
(OR8To4 G8RC:$in, G8RC:$in)>;
// SHL/SRL
-def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
+def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
-def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
+def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
// Hi and Lo for Darwin Global Addresses.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 900ca1a..4fd4533 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -252,7 +252,7 @@
def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
"UPDATE_VRSAVE $rD, $rS", []>;
}
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
+def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
[(set GPRC:$rD, (undef))]>;
def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
[(set F8RC:$rD, (undef))]>;