Implement a few more binary encoding bits. Still very early stage proof-of-
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll
index af7cf71..2da4e74 100644
--- a/test/MC/ARM/simple-encoding.ll
+++ b/test/MC/ARM/simple-encoding.ll
@@ -9,10 +9,18 @@
entry:
; CHECK: foo
; CHECK: 0xf0,0x00,0xf0,0x07
-; CHECK: 0x1e,0xff,0x2f,0x01
+; CHECK: 0x1e,0xff,0x2f,0xe1
tail call void @llvm.trap()
ret i32 undef
}
+define i32 @f2(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK: f2
+; CHECK: 0x00,0x00,0x81,0xe0
+; CHECK: 0x1e,0xff,0x2f,0xe1
+ %add = add nsw i32 %b, %a
+ ret i32 %add
+}
declare void @llvm.trap() nounwind