Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll
index 82eeafd..277cf07 100644
--- a/test/CodeGen/X86/mmx-shift.ll
+++ b/test/CodeGen/X86/mmx-shift.ll
@@ -1,6 +1,7 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psllq | grep 32
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psllq | grep 32
; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psrad
+; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psrlw
define i64 @t1(<1 x i64> %mm1) nounwind {
entry:
@@ -19,3 +20,13 @@
}
declare <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32>, <2 x i32>) nounwind readnone
+
+define i64 @t3(<1 x i64> %mm1, i32 %bits) nounwind {
+entry:
+ %tmp6 = bitcast <1 x i64> %mm1 to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp8 = tail call <4 x i16> @llvm.x86.mmx.psrli.w( <4 x i16> %tmp6, i32 %bits ) nounwind readnone ; <<4 x i16>> [#uses=1]
+ %retval1314 = bitcast <4 x i16> %tmp8 to i64 ; <i64> [#uses=1]
+ ret i64 %retval1314
+}
+
+declare <4 x i16> @llvm.x86.mmx.psrli.w(<4 x i16>, i32) nounwind readnone