implement uncond branch insertion, mark branches with isBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31160 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 810c254..c61d836 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -48,3 +48,11 @@
}
return false;
}
+
+void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ const std::vector<MachineOperand> &Cond)const{
+ // Can only insert uncond branches so far.
+ assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
+ BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+}
\ No newline at end of file
diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 6318caa..0621c70 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -40,6 +40,10 @@
///
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const;
+
+ virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ const std::vector<MachineOperand> &Cond) const;
};
}
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 816970f..f2100e1 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -227,7 +227,7 @@
def UMULL : IntBinOp<"umull r12,", mulhu>;
}
-let isTerminator = 1 in {
+let isTerminator = 1, isBranch = 1 in {
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
"b$cc $dst",
[(armbr bb:$dst, imm:$cc)]>;