diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 1a07013..d9443c8 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -206,10 +206,8 @@
   MachineBasicBlock *MBB = Fn.begin();
   MachineBasicBlock::iterator I = MBB->begin();
   for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
-    const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
-
-    // Insert the spill to the stack frame...
-    RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i], RC);
+    // Insert the spill to the stack frame.
+    RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
   }
 
   // Add code to restore the callee-save registers in each exiting block.
@@ -221,8 +219,7 @@
       I = MBB->end(); --I;
 
       for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
-        const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
-        RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i], RC);
+        RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i]);
         --I;  // Insert in reverse order
       }
     }
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index bea603c..68d5fd9 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -267,7 +267,7 @@
     const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DEBUG(std::cerr << " to stack slot #" << FrameIndex);
-    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
+    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
     ++NumStores;   // Update statistics
   }
 
@@ -506,7 +506,7 @@
                   << RegInfo->getName(PhysReg) << "\n");
 
   // Add move instruction(s)
-  RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
+  RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
   ++NumLoads;    // Update statistics
 
   MI->SetMachineOperandReg(OpNum, PhysReg);  // Assign the input register
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 4c1e371..320b267 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -131,7 +131,7 @@
 
   // Add move instruction(s)
   ++NumLoads;
-  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
   return PhysReg;
 }
 
@@ -143,7 +143,7 @@
 
   // Add move instruction(s)
   ++NumStores;
-  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
 }
 
 
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 572bace..e84652e 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -144,8 +144,7 @@
                                     *mbbi,
                                     mii,
                                     physReg,
-                                    vrm.getStackSlot(virtReg),
-                                    mf.getSSARegMap()->getRegClass(virtReg));
+                                    vrm.getStackSlot(virtReg));
                                 loaded[virtReg] = true;
                                 DEBUG(std::cerr << '\t';
                                       prior(mii)->print(std::cerr, &tm));
@@ -157,8 +156,7 @@
                                     *mbbi,
                                     next(mii),
                                     physReg,
-                                    vrm.getStackSlot(virtReg),
-                                    mf.getSSARegMap()->getRegClass(virtReg));
+                                    vrm.getStackSlot(virtReg));
                                 ++numStores;
                             }
                             mii->SetMachineOperandReg(i, physReg);
@@ -226,8 +224,7 @@
                 mri_->storeRegToStackSlot(*lastDef->getParent(),
                                           nextLastRef,
                                           physReg,
-                                          vrm_->getStackSlot(virtReg),
-                                          mri_->getRegClass(physReg));
+                                          vrm_->getStackSlot(virtReg));
                 ++numStores;
                 DEBUG(std::cerr << "added: ";
                       prior(nextLastRef)->print(std::cerr, tm_);
@@ -258,8 +255,7 @@
                 // load if necessary
                 if (vrm_->hasStackSlot(virtReg)) {
                     mri_->loadRegFromStackSlot(mbb, mii, physReg,
-                                               vrm_->getStackSlot(virtReg),
-                                               mri_->getRegClass(physReg));
+                                               vrm_->getStackSlot(virtReg));
                     ++numLoads;
                     DEBUG(std::cerr << "added: ";
                           prior(mii)->print(std::cerr, tm_));
diff --git a/lib/Target/PowerPC/PowerPCRegisterInfo.cpp b/lib/Target/PowerPC/PowerPCRegisterInfo.cpp
index 94430d5..b1e3dd2 100644
--- a/lib/Target/PowerPC/PowerPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PowerPCRegisterInfo.cpp
@@ -71,11 +71,12 @@
 int 
 PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
-                                         unsigned SrcReg, int FrameIdx,
-                                         const TargetRegisterClass *RC) const {
+                                         unsigned SrcReg, int FrameIdx) const {
+  const TargetRegisterClass *RC = getRegClass(SrcReg);
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD 
   };
+
   unsigned OC = Opcode[getIdx(RC)];
   if (SrcReg == PPC::LR) {
     MBB.insert(MI, BuildMI(PPC::MFLR, 0, PPC::R0));
@@ -91,11 +92,11 @@
 int 
 PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
-                                          unsigned DestReg, int FrameIdx,
-                                          const TargetRegisterClass *RC) const {
+                                          unsigned DestReg, int FrameIdx) const{
   static const unsigned Opcode[] = { 
     PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD 
   };
+  const TargetRegisterClass *RC = getRegClass(DestReg);
   unsigned OC = Opcode[getIdx(RC)];
   if (DestReg == PPC::LR) {
     MBB.insert(MI, addFrameReference(BuildMI(OC, 2, PPC::R0), FrameIdx));
diff --git a/lib/Target/PowerPC/PowerPCRegisterInfo.h b/lib/Target/PowerPC/PowerPCRegisterInfo.h
index 45db650..dfa571b 100644
--- a/lib/Target/PowerPC/PowerPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PowerPCRegisterInfo.h
@@ -32,13 +32,11 @@
   /// Code Generation virtual methods...
   int storeRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI,
-                          unsigned SrcReg, int FrameIndex,
-                          const TargetRegisterClass *RC) const;
+                          unsigned SrcReg, int FrameIndex) const;
 
   int loadRegFromStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
-                           unsigned DestReg, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
+                           unsigned DestReg, int FrameIndex) const;
   
   int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 		   unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/Skeleton/SkeletonRegisterInfo.cpp b/lib/Target/Skeleton/SkeletonRegisterInfo.cpp
index bb4651b..7c8ea10 100644
--- a/lib/Target/Skeleton/SkeletonRegisterInfo.cpp
+++ b/lib/Target/Skeleton/SkeletonRegisterInfo.cpp
@@ -20,18 +20,16 @@
   : SkeletonGenRegisterInfo(Skeleton::ADJCALLSTACKDOWN,
                            Skeleton::ADJCALLSTACKUP) {}
 
-int SkeletonRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
-                                              MachineBasicBlock::iterator MBBI,
-                                              unsigned SrcReg, int FrameIdx,
-                                          const TargetRegisterClass *RC) const {
+int SkeletonRegisterInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+                    unsigned SrcReg, int FrameIdx) const {
   abort();
   return -1;
 }
 
-int SkeletonRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                               MachineBasicBlock::iterator MBBI,
-                                               unsigned DestReg, int FrameIdx,
-                                          const TargetRegisterClass *RC) const {
+int SkeletonRegisterInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+                     unsigned DestReg, int FrameIdx) const {
   abort();
   return -1;
 }
diff --git a/lib/Target/Skeleton/SkeletonRegisterInfo.h b/lib/Target/Skeleton/SkeletonRegisterInfo.h
index af8526f..3bf5766 100644
--- a/lib/Target/Skeleton/SkeletonRegisterInfo.h
+++ b/lib/Target/Skeleton/SkeletonRegisterInfo.h
@@ -27,13 +27,11 @@
     // See MRegisterInfo.h for information on these methods.
     int storeRegToStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
-                            unsigned SrcReg, int FrameIndex,
-                            const TargetRegisterClass *RC) const;
+                            unsigned SrcReg, int FrameIndex) const;
     
     int loadRegFromStackSlot(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MBBI,
-                             unsigned DestReg, int FrameIndex,
-                             const TargetRegisterClass *RC) const;
+                             unsigned DestReg, int FrameIndex) const;
     
     int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                      unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index c2c7da8..ef4d178 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -25,12 +25,11 @@
   : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
                            V8::ADJCALLSTACKUP) {}
 
-int SparcV8RegisterInfo::storeRegToStackSlot(
-  MachineBasicBlock &MBB,
-  MachineBasicBlock::iterator I,
-  unsigned SrcReg, int FrameIdx,
-  const TargetRegisterClass *RC) const
-{
+int SparcV8RegisterInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                    unsigned SrcReg, int FrameIdx) const {
+  const TargetRegisterClass *RC = getRegClass(SrcReg);
+
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
   if (RC == SparcV8::IntRegsRegisterClass) 
     BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
@@ -46,12 +45,10 @@
   return 1;
 }
 
-int SparcV8RegisterInfo::loadRegFromStackSlot(
-  MachineBasicBlock &MBB,
-  MachineBasicBlock::iterator I,
-  unsigned DestReg, int FrameIdx,
-  const TargetRegisterClass *RC) const
-{
+int SparcV8RegisterInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                     unsigned DestReg, int FrameIdx) const {
+  const TargetRegisterClass *RC = getRegClass(DestReg);
   if (RC == SparcV8::IntRegsRegisterClass) 
     BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
   else if (RC == SparcV8::FPRegsRegisterClass)
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 1481f5f..e4dcacc 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -28,13 +28,11 @@
   /// Code Generation virtual methods...
   int storeRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI,
-                          unsigned SrcReg, int FrameIndex,
-                          const TargetRegisterClass *RC) const;
+                          unsigned SrcReg, int FrameIndex) const;
 
   int loadRegFromStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
-                           unsigned DestReg, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
+                           unsigned DestReg, int FrameIndex) const;
   
   int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 		   unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index c2c7da8..ef4d178 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -25,12 +25,11 @@
   : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
                            V8::ADJCALLSTACKUP) {}
 
-int SparcV8RegisterInfo::storeRegToStackSlot(
-  MachineBasicBlock &MBB,
-  MachineBasicBlock::iterator I,
-  unsigned SrcReg, int FrameIdx,
-  const TargetRegisterClass *RC) const
-{
+int SparcV8RegisterInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                    unsigned SrcReg, int FrameIdx) const {
+  const TargetRegisterClass *RC = getRegClass(SrcReg);
+
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
   if (RC == SparcV8::IntRegsRegisterClass) 
     BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
@@ -46,12 +45,10 @@
   return 1;
 }
 
-int SparcV8RegisterInfo::loadRegFromStackSlot(
-  MachineBasicBlock &MBB,
-  MachineBasicBlock::iterator I,
-  unsigned DestReg, int FrameIdx,
-  const TargetRegisterClass *RC) const
-{
+int SparcV8RegisterInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                     unsigned DestReg, int FrameIdx) const {
+  const TargetRegisterClass *RC = getRegClass(DestReg);
   if (RC == SparcV8::IntRegsRegisterClass) 
     BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
   else if (RC == SparcV8::FPRegsRegisterClass)
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.h b/lib/Target/SparcV8/SparcV8RegisterInfo.h
index 1481f5f..e4dcacc 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.h
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.h
@@ -28,13 +28,11 @@
   /// Code Generation virtual methods...
   int storeRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI,
-                          unsigned SrcReg, int FrameIndex,
-                          const TargetRegisterClass *RC) const;
+                          unsigned SrcReg, int FrameIndex) const;
 
   int loadRegFromStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
-                           unsigned DestReg, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
+                           unsigned DestReg, int FrameIndex) const;
   
   int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 		   unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/SparcV9/SparcV9RegisterInfo.cpp b/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
index bf8717e..1b0fc72 100644
--- a/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
@@ -278,15 +278,13 @@
 
 int SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
-                                         unsigned SrcReg, int FrameIndex,
-                                         const TargetRegisterClass *RC) const {
+                                         unsigned SrcReg, int FrameIndex) const{
   abort ();
 }
 
 int SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
-                                          unsigned DestReg, int FrameIndex,
-                                          const TargetRegisterClass *RC) const {
+                                          unsigned DestReg, int FrameIndex) const {
   abort ();
 }
 
diff --git a/lib/Target/SparcV9/SparcV9RegisterInfo.h b/lib/Target/SparcV9/SparcV9RegisterInfo.h
index 6b86c88..bd31bb1 100644
--- a/lib/Target/SparcV9/SparcV9RegisterInfo.h
+++ b/lib/Target/SparcV9/SparcV9RegisterInfo.h
@@ -27,12 +27,10 @@
   // The rest of these are stubs... for now.
   int storeRegToStackSlot (MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
-                           unsigned SrcReg, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
+                           unsigned SrcReg, int FrameIndex) const;
   int loadRegFromStackSlot (MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
-                            unsigned DestReg, int FrameIndex,
-                            const TargetRegisterClass *RC) const;
+                            unsigned DestReg, int FrameIndex) const;
   int copyRegToReg (MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,
                     unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index dba98d6..6890cbe 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -56,10 +56,10 @@
 
 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
-                                         unsigned SrcReg, int FrameIdx,
-                                         const TargetRegisterClass *RC) const {
+                                         unsigned SrcReg, int FrameIdx) const {
   static const unsigned Opcode[] =
     { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m };
+  const TargetRegisterClass *RC = getRegClass(SrcReg);
   MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
 				       FrameIdx).addReg(SrcReg);
   MBB.insert(MI, I);
@@ -68,10 +68,10 @@
 
 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
-                                          unsigned DestReg, int FrameIdx,
-                                          const TargetRegisterClass *RC) const{
+                                          unsigned DestReg, int FrameIdx) const{
   static const unsigned Opcode[] =
     { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m };
+  const TargetRegisterClass *RC = getRegClass(DestReg);
   unsigned OC = Opcode[getIdx(RC)];
   MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
   return 1;
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index a582519..2839556 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -29,13 +29,11 @@
   /// Code Generation virtual methods...
   int storeRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
-                          unsigned SrcReg, int FrameIndex,
-                          const TargetRegisterClass *RC) const;
+                          unsigned SrcReg, int FrameIndex) const;
 
   int loadRegFromStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
-                           unsigned DestReg, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
+                           unsigned DestReg, int FrameIndex) const;
   
   int copyRegToReg(MachineBasicBlock &MBB,
                    MachineBasicBlock::iterator MI,