Change ConstantPoolSDNode to actually hold the Constant itself instead of
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23081 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 20236f8..33c9167 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAG.h"
@@ -38,12 +39,14 @@
const TargetInstrInfo &TII;
const MRegisterInfo &MRI;
SSARegMap *RegMap;
+ MachineConstantPool *ConstPool;
std::map<SDNode *, unsigned> EmittedOps;
public:
SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
- MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
+ MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
+ ConstPool(BB->getParent()->getConstantPool()) {
assert(&TII && "Target doesn't provide instr info?");
assert(&MRI && "Target doesn't provide register info?");
}
@@ -148,7 +151,8 @@
MI->addFrameIndexOperand(FI->getIndex());
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(Op.getOperand(i))) {
- MI->addConstantPoolIndexOperand(CP->getIndex());
+ unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
+ MI->addConstantPoolIndexOperand(Idx);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op.getOperand(i))) {
MI->addExternalSymbolOperand(ES->getSymbol(), false);