commit 58bbb81764ccd20d06018b407d2698e4f1ad0709
author Craig Topper <craig.topper@gmail.com> Tue Sep 13 06:54:58 2011 +0000
committer Craig Topper <craig.topper@gmail.com> Tue Sep 13 06:54:58 2011 +0000
tree b2394788bca9f7b6fcdc0e5c8029224d8792bbbd
parent 6b0b2d6c4174536cedd04e912600237618d41817

Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrSSE.td

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index bb4597b..c5ec346 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -3258,6 +3258,18 @@
 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
                     "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
 
+// For Disassembler
+let isCodeGenOnly = 1 in {
+def VMOVDQArr_REV  : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                        "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
+                        "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+def VMOVDQUrr_REV  : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                        "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
+def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
+                        "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
+}
+
 let canFoldAsLoad = 1, mayLoad = 1 in {
 def VMOVDQArm  : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                    "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
@@ -3294,6 +3306,16 @@
                    "movdqu\t{$src, $dst|$dst, $src}",
                    []>, XS, Requires<[HasSSE2]>;
 
+// For Disassembler
+let isCodeGenOnly = 1 in {
+def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                       "movdqa\t{$src, $dst|$dst, $src}", []>;
+
+def MOVDQUrr_REV :   I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                       "movdqu\t{$src, $dst|$dst, $src}",
+                       []>, XS, Requires<[HasSSE2]>;
+}
+
 let canFoldAsLoad = 1, mayLoad = 1 in {
 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                    "movdqa\t{$src, $dst|$dst, $src}",

test/MC/Disassembler/X86/simple-tests.txt

diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 002e202..f431324 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -199,37 +199,73 @@
 0x66 0x0f 0x29 0xc1
 
 # CHECK: vmovups %xmm1, %xmm0
-0xc5 0xf0 0x10 0xc1
+0xc5 0xf8 0x10 0xc1
 
 # CHECK: vmovups %xmm0, %xmm1
-0xc5 0xf0 0x11 0xc1
+0xc5 0xf8 0x11 0xc1
 
 # CHECK: vmovaps %xmm1, %xmm0
-0xc5 0xf0 0x28 0xc1
+0xc5 0xf8 0x28 0xc1
 
 # CHECK: vmovaps %xmm0, %xmm1
-0xc5 0xf0 0x29 0xc1
+0xc5 0xf8 0x29 0xc1
 
 # CHECK: vmovupd %xmm1, %xmm0
-0xc5 0xf1 0x10 0xc1
+0xc5 0xf9 0x10 0xc1
 
 # CHECK: vmovupd %xmm0, %xmm1
-0xc5 0xf1 0x11 0xc1
+0xc5 0xf9 0x11 0xc1
 
 # CHECK: vmovapd %xmm1, %xmm0
-0xc5 0xf1 0x28 0xc1
+0xc5 0xf9 0x28 0xc1
 
 # CHECK: vmovapd %xmm0, %xmm1
-0xc5 0xf1 0x29 0xc1
+0xc5 0xf9 0x29 0xc1
 
 # CHECK: vmovups %ymm1, %ymm0
-0xc5 0xf4 0x10 0xc1
+0xc5 0xfc 0x10 0xc1
 
 # CHECK: vmovups %ymm0, %ymm1
-0xc5 0xf4 0x11 0xc1
+0xc5 0xfc 0x11 0xc1
 
 # CHECK: vmovaps %ymm1, %ymm0
-0xc5 0xf4 0x28 0xc1
+0xc5 0xfc 0x28 0xc1
 
 # CHECK: vmovaps %ymm0, %ymm1
-0xc5 0xf4 0x29 0xc1
+0xc5 0xfc 0x29 0xc1
+
+# CHECK: movdqa %xmm1, %xmm0
+0x66 0x0f 0x6f 0xc1
+
+# CHECK: movdqa %xmm0, %xmm1
+0x66 0x0f 0x7f 0xc1
+
+# CHECK: movdqu %xmm1, %xmm0
+0xf3 0x0f 0x6f 0xc1
+
+# CHECK: movdqu %xmm0, %xmm1
+0xf3 0x0f 0x7f 0xc1
+
+# CHECK: vmovdqa %xmm1, %xmm0
+0xc5 0xf9 0x6f 0xc1
+
+# CHECK: vmovdqa %xmm0, %xmm1
+0xc5 0xf9 0x7f 0xc1
+
+# CHECK: vmovdqa %ymm1, %ymm0
+0xc5 0xfd 0x6f 0xc1
+
+# CHECK: vmovdqa %ymm0, %ymm1
+0xc5 0xfd 0x7f 0xc1
+
+# CHECK: vmovdqu %xmm1, %xmm0
+0xc5 0xfa 0x6f 0xc1
+
+# CHECK: vmovdqu %xmm0, %xmm1
+0xc5 0xfa 0x7f 0xc1
+
+# CHECK: vmovdqu %ymm1, %ymm0
+0xc5 0xfe 0x6f 0xc1
+
+# CHECK: vmovdqu %ymm0, %ymm1
+0xc5 0xfe 0x7f 0xc1

utils/TableGen/X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 23c0fa8..5338d56 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -354,9 +354,7 @@
     
   // TEMPORARY pending bug fixes
 
-  if (Name.find("VMOVDQU") != Name.npos ||
-      Name.find("VMOVDQA") != Name.npos ||
-      Name.find("VROUND") != Name.npos)
+  if (Name.find("VROUND") != Name.npos)
     return FILTER_STRONG;
     
   // Filter out artificial instructions