commit 591ec57c094b2524832fdc940cb387918d4bf976
author Andrew Lenharth <andrewl@lenharth.org> Tue May 31 18:42:18 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Tue May 31 18:42:18 2005 +0000
tree 1d60812517d34af5e0d1ebab843f086436e5d83d
parent 14f30c927dd6ad12974df653c681d21524c532f1

switch to the new live in thing.  Really, this time it works


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22187 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index deed190..453754c 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -210,7 +210,7 @@
       case MVT::i16:
       case MVT::i32:
       case MVT::i64:
-        args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT));
+        args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
         argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
         if (VT != MVT::i64)
           argt = DAG.getNode(ISD::TRUNCATE, VT, argt);