Silence unused variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59841 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Archive/ArchiveWriter.cpp b/lib/Archive/ArchiveWriter.cpp
index 2269464..336a2bd 100644
--- a/lib/Archive/ArchiveWriter.cpp
+++ b/lib/Archive/ArchiveWriter.cpp
@@ -306,8 +306,10 @@
// Write the header
ARFile.write((char*)&Hdr, sizeof(Hdr));
+#ifndef NDEBUG
// Save the starting position of the symbol tables data content.
unsigned startpos = ARFile.tellp();
+#endif
// Write out the symbols sequentially
for ( Archive::SymTabType::iterator I = symTab.begin(), E = symTab.end();
@@ -321,8 +323,10 @@
ARFile.write(I->first.data(), I->first.length());
}
+#ifndef NDEBUG
// Now that we're done with the symbol table, get the ending file position
unsigned endpos = ARFile.tellp();
+#endif
// Make sure that the amount we wrote is what we pre-computed. This is
// critical for file integrity purposes.
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index a512912..2a979e1 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -125,6 +125,7 @@
I != E; ++I) {
bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
+ inserted = true;
i2miMap_.push_back(I);
MIIndex += InstrSlots::NUM;
FunctionSize++;
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 9fe42f6..ecfebc5 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -678,6 +678,7 @@
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
+ removed = true;
}
}
}
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 6ee955d..6d7c5cc 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -152,7 +152,9 @@
MI->getOperand(3).isImm() && "Invalid insert_subreg");
unsigned DstReg = MI->getOperand(0).getReg();
+#ifndef NDEBUG
unsigned SrcReg = MI->getOperand(1).getReg();
+#endif
unsigned InsReg = MI->getOperand(2).getReg();
unsigned SubIdx = MI->getOperand(3).getImm();
diff --git a/lib/Transforms/Scalar/PredicateSimplifier.cpp b/lib/Transforms/Scalar/PredicateSimplifier.cpp
index f5c68ab..a7e4d6e 100644
--- a/lib/Transforms/Scalar/PredicateSimplifier.cpp
+++ b/lib/Transforms/Scalar/PredicateSimplifier.cpp
@@ -341,6 +341,7 @@
UGE = UGT | EQ_BIT
};
+#ifndef NDEBUG
/// validPredicate - determines whether a given value is actually a lattice
/// value. Only used in assertions or debugging.
static bool validPredicate(LatticeVal LV) {
@@ -355,6 +356,7 @@
return false;
}
}
+#endif
/// reversePredicate - reverse the direction of the inequality
static LatticeVal reversePredicate(LatticeVal LV) {
diff --git a/lib/Transforms/Scalar/Reassociate.cpp b/lib/Transforms/Scalar/Reassociate.cpp
index 313723c..c220c2b 100644
--- a/lib/Transforms/Scalar/Reassociate.cpp
+++ b/lib/Transforms/Scalar/Reassociate.cpp
@@ -53,6 +53,7 @@
}
}
+#ifndef DEBUG
/// PrintOps - Print out the expression identified in the Ops list.
///
static void PrintOps(Instruction *I, const std::vector<ValueEntry> &Ops) {
@@ -64,6 +65,7 @@
cerr << "," << Ops[i].Rank;
}
}
+#endif
namespace {
class VISIBILITY_HIDDEN Reassociate : public FunctionPass {
@@ -282,6 +284,7 @@
std::swap(LHS, RHS);
bool Success = !I->swapOperands();
assert(Success && "swapOperands failed");
+ Success = false;
MadeChange = true;
}
} else if (RHSBO) {
diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp
index 3e08b59..66caf5f 100644
--- a/lib/VMCore/Instructions.cpp
+++ b/lib/VMCore/Instructions.cpp
@@ -2204,6 +2204,7 @@
if (const VectorType *SrcPTy = dyn_cast<VectorType>(SrcTy)) {
assert(DestPTy->getBitWidth() == SrcPTy->getBitWidth() &&
"Casting vector to vector of different widths");
+ SrcPTy = NULL;
return BitCast; // vector -> vector
} else if (DestPTy->getBitWidth() == SrcBits) {
return BitCast; // float/int -> vector