diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index ac573c4..3d65a53 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -109,9 +109,8 @@
   /// srl/add/sra.
   bool isPow2DivCheap() const { return Pow2DivIsCheap; }
 
-  /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
-  ///
-  MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
+  /// getSetCCResultType - Return the ValueType of the result of setcc operations.
+  virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
 
   /// getSetCCResultContents - For targets without boolean registers, this flag
   /// returns information about the contents of the high-bits in the setcc
@@ -707,10 +706,6 @@
   /// amounts.  This type defaults to the pointer type.
   void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
 
-  /// setSetCCResultType - Describe the type that shoudl be used as the result
-  /// of a setcc operation.  This defaults to the pointer type.
-  void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
-
   /// setSetCCResultContents - Specify how the target extends the result of a
   /// setcc operation in a register.
   void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
@@ -1259,10 +1254,6 @@
   /// it.
   bool Pow2DivIsCheap;
   
-  /// SetCCResultTy - The type that SetCC operations use.  This defaults to the
-  /// PointerTy.
-  MVT::ValueType SetCCResultTy;
-
   /// SetCCResultContents - Information about the contents of the high-bits in
   /// the result of a setcc comparison operation.
   SetCCResultValue SetCCResultContents;
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3a8c468..5cda144 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2605,7 +2605,7 @@
     return N2;
   
   // Determine if the condition we're dealing with is constant
-  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
+  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
   if (SCC.Val) AddToWorkList(SCC.Val);
 
   if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
@@ -5077,7 +5077,7 @@
   ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
 
   // Determine if the condition we're dealing with is constant
-  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
+  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
   if (SCC.Val) AddToWorkList(SCC.Val);
   ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
 
@@ -5157,7 +5157,7 @@
     SDOperand Temp, SCC;
     // cast from setcc result type to select result type
     if (AfterLegalize) {
-      SCC  = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
+      SCC  = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
       if (N2.getValueType() < SCC.getValueType())
         Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
       else
@@ -5182,8 +5182,8 @@
   // otherwise, go ahead with the folds.
   if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
     MVT::ValueType XType = N0.getValueType();
-    if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
-      SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
+    if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
+      SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
       if (Res.getValueType() != VT)
         Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
       return Res;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4993e46..abd569b 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3186,7 +3186,7 @@
         MVT::ValueType IVT = 
           Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
         SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
-        SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
+        SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
                                SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
         // Get the absolute value of the result.
         SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
@@ -3522,7 +3522,7 @@
         break;
       case ISD::CTTZ:
         //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
-        Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
+        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
                             DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
                             ISD::SETEQ);
         Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
@@ -3574,7 +3574,8 @@
         // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
         MVT::ValueType VT = Node->getValueType(0);
         Tmp2 = DAG.getConstantFP(0.0, VT);
-        Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
+        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
+			    ISD::SETUGT);
         Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
         Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
         break;
@@ -3780,7 +3781,7 @@
           APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
           (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
           Tmp2 = DAG.getConstantFP(apf, VT);
-          Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
+          Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
                             Node->getOperand(0), Tmp2, ISD::SETLT);
           True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
           False = DAG.getNode(ISD::FP_TO_SINT, NVT,
@@ -4124,9 +4125,12 @@
     break;
 
   case ISD::SETCC:
-    assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
-    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
-                         Node->getOperand(1), Node->getOperand(2));
+    assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
+	   && "SetCC type is not legal??");
+    Result = DAG.getNode(ISD::SETCC,
+			 TLI.getSetCCResultType(Node->getOperand(0)),
+	                 Node->getOperand(0), Node->getOperand(1),
+			 Node->getOperand(2));
     break;
     
   case ISD::TRUNCATE:
@@ -4484,7 +4488,7 @@
       break;
     case ISD::CTTZ:
       // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
-      Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
                           DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
                           ISD::SETEQ);
       Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
@@ -4748,11 +4752,12 @@
       Tmp2 = DAG.getConstant(0, MVT::i32);
       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
       if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
-        Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
+        Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
+			   CC);
         LHS = ExpandLibCall(TLI.getLibcallName(LC2),
                             DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 
                             false /*sign irrelevant*/, Dummy);
-        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
+        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
                            DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
         Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
         Tmp2 = SDOperand();
@@ -4773,11 +4778,11 @@
       //         BNE crN, L:
       //         FCMP crN, lo1, lo2
       // The following can be improved, but not that much.
-      Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
-      Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
       Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
-      Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
-      Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
       Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
       Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
       Tmp2 = SDOperand();
@@ -4835,14 +4840,15 @@
       // NOTE: on targets without efficient SELECT of bools, we can always use
       // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
       TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
-      Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
-                               false, DagCombineInfo);
+      Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
+			       LowCC, false, DagCombineInfo);
       if (!Tmp1.Val)
-        Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
-      Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
+        Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
+      Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                                CCCode, false, DagCombineInfo);
       if (!Tmp2.Val)
-        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
+        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
+			   RHSHi,CC);
       
       ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
       ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
@@ -4859,10 +4865,11 @@
         Tmp1 = Tmp2;
         Tmp2 = SDOperand();
       } else {
-        Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
+        Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                                    ISD::SETEQ, false, DagCombineInfo);
         if (!Result.Val)
-          Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
+          Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
+			      ISD::SETEQ);
         Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
                                         Result, Tmp1, Tmp2));
         Tmp1 = Result;
@@ -5336,7 +5343,7 @@
     SDOperand SignedConv = ExpandIntToFP(true, DestTy,
                    DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi));
 
-    SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
+    SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
                                      DAG.getConstant(0, Hi.getValueType()),
                                      ISD::SETLT);
     SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
@@ -5489,7 +5496,7 @@
   assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
   SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
 
-  SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
+  SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
                                    DAG.getConstant(0, Op0.getValueType()),
                                    ISD::SETLT);
   SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
@@ -5895,7 +5902,7 @@
     ExpandOp(Node->getOperand(0), Lo, Hi);
     SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
     SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
-    SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
+    SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
                                         ISD::SETNE);
     SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
     LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
@@ -5910,7 +5917,7 @@
     ExpandOp(Node->getOperand(0), Lo, Hi);
     SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
     SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
-    SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
+    SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
                                         ISD::SETNE);
     SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
     HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
index d720e81..61ab510 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
@@ -632,7 +632,7 @@
   GetExpandedOp(N->getOperand(0), Lo, Hi);
   MVT::ValueType NVT = Lo.getValueType();
 
-  SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
+  SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
                                      DAG.getConstant(0, NVT), ISD::SETNE);
 
   SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
@@ -660,7 +660,7 @@
   GetExpandedOp(N->getOperand(0), Lo, Hi);
   MVT::ValueType NVT = Lo.getValueType();
 
-  SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Lo,
+  SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
                                      DAG.getConstant(0, NVT), ISD::SETNE);
 
   SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
@@ -1031,7 +1031,7 @@
   SDOperand Lo, Hi;
   GetExpandedOp(Source, Lo, Hi);
   
-  SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
+  SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
                                    DAG.getConstant(0, Hi.getValueType()),
                                    ISD::SETLT);
   SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
@@ -1113,11 +1113,11 @@
     //         FCMP crN, lo1, lo2
     // The following can be improved, but not that much.
     SDOperand Tmp1, Tmp2, Tmp3;
-    Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
-    Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
+    Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
+    Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
     Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
-    Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
-    Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
+    Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
+    Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
     Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
     NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
     NewRHS = SDOperand();   // LHS is the result, not a compare.
@@ -1174,14 +1174,14 @@
   // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
   TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
   SDOperand Tmp1, Tmp2;
-  Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
+  Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
                            false, DagCombineInfo);
   if (!Tmp1.Val)
-    Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
-  Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
+    Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
+  Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                            CCCode, false, DagCombineInfo);
   if (!Tmp2.Val)
-    Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,
+    Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                        DAG.getCondCode(CCCode));
   
   ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
@@ -1201,10 +1201,11 @@
     return;
   }
   
-  NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
+  NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                              ISD::SETEQ, false, DagCombineInfo);
   if (!NewLHS.Val)
-    NewLHS = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
+    NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
+			  ISD::SETEQ);
   NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
                        NewLHS, Tmp1, Tmp2);
   NewRHS = SDOperand();
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
index f3232fc..2b1a29d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
@@ -186,9 +186,10 @@
 }
 
 SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
-  assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
-  return DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), N->getOperand(0),
-                     N->getOperand(1), N->getOperand(2));
+  assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
+	 && "SetCC type is not legal??");
+  return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
+		     N->getOperand(0), N->getOperand(1), N->getOperand(2));
 }
 
 SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 85fbb6f..bb4b959 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1440,7 +1440,7 @@
   // Emit the range check for the jump table, and branch to the default
   // block for the switch statement if the value being switched on exceeds
   // the largest case in the switch.
-  SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
+  SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
                                DAG.getConstant(JTH.Last-JTH.First,VT),
                                ISD::SETUGT);
 
@@ -1473,7 +1473,7 @@
                               DAG.getConstant(B.First, VT));
 
   // Check range
-  SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
+  SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
                                     DAG.getConstant(B.Range, VT),
                                     ISD::SETUGT);
 
@@ -1526,7 +1526,7 @@
                                 SwitchVal,
                                 DAG.getConstant(B.Mask,
                                                 TLI.getPointerTy()));
-  SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
+  SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
                                   DAG.getConstant(0, TLI.getPointerTy()),
                                   ISD::SETNE);
   SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 351fe81..0025766 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -191,7 +191,7 @@
     
   IsLittleEndian = TD->isLittleEndian();
   UsesGlobalOffsetTable = false;
-  ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
+  ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
   ShiftAmtHandling = Undefined;
   memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
   memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
@@ -372,6 +372,13 @@
   return NULL;
 }
 
+
+MVT::ValueType
+TargetLowering::getSetCCResultType(const SDOperand &) const {
+  return getValueType(TD->getIntPtrType());
+}
+
+
 /// getVectorTypeBreakdown - Vector types are broken down into some number of
 /// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 368c736..87f1eec 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -40,7 +40,6 @@
   // Set up the TargetLowering object.
   //I am having problems with shr n ubyte 1
   setShiftAmountType(MVT::i64);
-  setSetCCResultType(MVT::i64);
   setSetCCResultContents(ZeroOrOneSetCCResult);
   
   setUsesGlobalOffsetTable(true);
@@ -151,6 +150,11 @@
   computeRegisterProperties();
 }
 
+MVT::ValueType
+AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
+  return MVT::i64;
+}
+
 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   default: return 0;
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 41a4b54..8738d02 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -66,6 +66,9 @@
   public:
     explicit AlphaTargetLowering(TargetMachine &TM);
     
+    /// getSetCCResultType - Get the SETCC result ValueType
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index a6147bf..b8f6ee3 100644
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -102,6 +102,9 @@
     /// getTargetNodeName() - This method returns the name of a target specific
     /// DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
+
+    /// getSetCCResultType - Return the ValueType for ISD::SETCC
+    MVT::ValueType getSetCCResultType(const SDOperand &) const;
     
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index e4d4867..dd330db 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -57,7 +57,6 @@
       // br.ret insn
       setOperationAction(ISD::RET, MVT::Other, Custom);
 
-      setSetCCResultType(MVT::i1);
       setShiftAmountType(MVT::i64);
 
       setOperationAction(ISD::FREM             , MVT::f32  , Expand);
@@ -137,6 +136,10 @@
   }
 }
   
+MVT::ValueType
+IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
+  return MVT::i1;
+}
 
 std::vector<SDOperand>
 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h
index 4f0630b..d0cf2a9 100644
--- a/lib/Target/IA64/IA64ISelLowering.h
+++ b/lib/Target/IA64/IA64ISelLowering.h
@@ -47,6 +47,7 @@
     unsigned VirtGPR; // this is public so it can be accessed in the selector
                       // for ISD::RET. add an accessor instead? FIXME
     const char *getTargetNodeName(unsigned Opcode) const;
+    MVT::ValueType getSetCCResultType(const SDOperand &) const;
       
     /// LowerArguments - This hook must be implemented to indicate how we should
     /// lower the arguments for the specified function, into the specified DAG.
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 5a0daf8..6e2a4f7 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -52,7 +52,6 @@
 {
   // Mips does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...). 
-  setSetCCResultType(MVT::i32);
   setSetCCResultContents(ZeroOrOneSetCCResult);
 
   // JumpTable targets must use GOT when using PIC_
@@ -112,6 +111,12 @@
 }
 
 
+MVT::ValueType
+MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
+  return MVT::i32;
+}
+
+
 SDOperand MipsTargetLowering::
 LowerOperation(SDOperand Op, SelectionDAG &DAG) 
 {
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 4af41d2..e2b4b3f 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -62,6 +62,9 @@
     //  DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
+    /// getSetCCResultType - get the ISD::SETCC result ValueType
+    MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
   private:
     // Lower Operand helpers
     SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 17c2838..56837b9 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -324,7 +324,6 @@
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
   }
   
-  setSetCCResultType(MVT::i32);
   setShiftAmountType(MVT::i32);
   setSetCCResultContents(ZeroOrOneSetCCResult);
   
@@ -407,6 +406,13 @@
   }
 }
 
+
+MVT::ValueType
+PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
+  return MVT::i32;
+}
+
+
 //===----------------------------------------------------------------------===//
 // Node matching predicates, for use by the tblgen matching code.
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 816ca8f..5229693 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -213,6 +213,9 @@
     /// DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
+    /// getSetCCResultType - Return the ISD::SETCC ValueType
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
     /// getPreIndexedAddressParts - returns true by value, base pointer and
     /// offset pointer and addressing mode by reference if the node's address
     /// can be legally represented as pre-indexed load / store address.
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 087c981..7b3b98f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -57,7 +57,6 @@
 
   // X86 is weird, it always uses i8 for shift amounts and setcc results.
   setShiftAmountType(MVT::i8);
-  setSetCCResultType(MVT::i8);
   setSetCCResultContents(ZeroOrOneSetCCResult);
   setSchedulingPreference(SchedulingForRegPressure);
   setShiftAmountFlavor(Mask);   // shl X, 32 == shl X, 0
@@ -728,6 +727,13 @@
   setPrefLoopAlignment(16);
 }
 
+
+MVT::ValueType
+X86TargetLowering::getSetCCResultType(const SDOperand &) const {
+  return MVT::i8;
+}
+
+
 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
 /// the desired ByVal argument alignment.
 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index c7bd507..cb8d94d 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -375,6 +375,9 @@
     /// DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
+    /// getSetCCResultType - Return the ISD::SETCC ValueType
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
     /// computeMaskedBitsForTargetNode - Determine which of the bits specified 
     /// in Mask are known to be either zero or one and return them in the 
     /// KnownZero/KnownOne bitsets.